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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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87d26d2d11
There is a possibility of a loop happening in the PLL output clock chain on the S3C64XX series. clk_mpll's parent was set to be clk_mout_mpll, but this is fed from clk_fout_epll (which is also clk_mpll). clk_mpll is meant to be the output from the MPLL, and clk_mout_mpll is a seperate clock derived from the mux of clk_mpll and clk_fin_mpll and thus should be considered a seperate clock. Anything using clk_mpll directly really should not be relying on this being the clock that is eventually routed to a peripheral, so remove the loop and ensure that the clocks accurately represent the clock chain in the device. The clk_mpll is not being used outside of the s3c6400-clock.c code, so this change should not break anything else. Do the same for the EPLL. Signed-off-by: Ben Dooks <ben-linux@fluff.org> |
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| .. | ||
| include/plat | ||
| clock.c | ||
| cpu.c | ||
| cpufreq.c | ||
| dev-audio.c | ||
| dev-uart.c | ||
| dma.c | ||
| gpiolib.c | ||
| irq-eint.c | ||
| irq-pm.c | ||
| irq.c | ||
| Kconfig | ||
| Makefile | ||
| pm.c | ||
| s3c6400-clock.c | ||
| s3c6400-init.c | ||
| setup-fb-24bpp.c | ||
| setup-i2c0.c | ||
| setup-i2c1.c | ||
| setup-sdhci-gpio.c | ||
| sleep.S | ||