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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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29ddd6e171
Allocate suspend/resume register storage based on the actual number registers the driver is aware of. The static allocation for register storage had fallen behind badly. Reported-by: Michael Bode <michael@bumbleB.de> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
177 lines
5.0 KiB
C
177 lines
5.0 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TILCDC_DRV_H__
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#define __TILCDC_DRV_H__
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/list.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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/* Defaulting to pixel clock defined on AM335x */
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#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
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/* Defaulting to max width as defined on AM335x */
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#define TILCDC_DEFAULT_MAX_WIDTH 2048
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/*
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* This may need some tweaking, but want to allow at least 1280x1024@60
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* with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
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* be supportable
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*/
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#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
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struct tilcdc_drm_private {
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void __iomem *mmio;
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struct clk *clk; /* functional clock */
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int rev; /* IP revision */
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/* don't attempt resolutions w/ higher W * H * Hz: */
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uint32_t max_bandwidth;
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/*
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* Pixel Clock will be restricted to some value as
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* defined in the device datasheet measured in KHz
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*/
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uint32_t max_pixelclock;
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/*
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* Max allowable width is limited on a per device basis
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* measured in pixels
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*/
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uint32_t max_width;
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/* register contents saved across suspend/resume: */
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u32 *saved_register;
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bool ctx_valid;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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unsigned int lcd_fck_rate;
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#endif
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struct workqueue_struct *wq;
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struct drm_fbdev_cma *fbdev;
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struct drm_crtc *crtc;
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unsigned int num_encoders;
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struct drm_encoder *encoders[8];
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unsigned int num_connectors;
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struct drm_connector *connectors[8];
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const struct drm_connector_helper_funcs *connector_funcs[8];
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bool is_componentized;
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};
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/* Sub-module for display. Since we don't know at compile time what panels
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* or display adapter(s) might be present (for ex, off chip dvi/tfp410,
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* hdmi encoder, various lcd panels), the connector/encoder(s) are split into
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* separate drivers. If they are probed and found to be present, they
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* register themselves with tilcdc_register_module().
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*/
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struct tilcdc_module;
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struct tilcdc_module_ops {
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/* create appropriate encoders/connectors: */
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int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
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#ifdef CONFIG_DEBUG_FS
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/* create debugfs nodes (can be NULL): */
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int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
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/* cleanup debugfs nodes (can be NULL): */
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void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
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#endif
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};
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struct tilcdc_module {
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const char *name;
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struct list_head list;
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const struct tilcdc_module_ops *funcs;
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unsigned int preferred_bpp;
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};
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void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
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const struct tilcdc_module_ops *funcs);
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void tilcdc_module_cleanup(struct tilcdc_module *mod);
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/* Panel config that needs to be set in the crtc, but is not coming from
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* the mode timings. The display module is expected to call
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* tilcdc_crtc_set_panel_info() to set this during modeset.
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*/
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struct tilcdc_panel_info {
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/* AC Bias Pin Frequency */
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uint32_t ac_bias;
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/* AC Bias Pin Transitions per Interrupt */
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uint32_t ac_bias_intrpt;
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/* DMA burst size */
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uint32_t dma_burst_sz;
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/* Bits per pixel */
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uint32_t bpp;
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/* FIFO DMA Request Delay */
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uint32_t fdd;
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/* TFT Alternative Signal Mapping (Only for active) */
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bool tft_alt_mode;
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/* Invert pixel clock */
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bool invert_pxl_clk;
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/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
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uint32_t sync_edge;
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/* Horizontal and Vertical Sync: Control: 0=ignore */
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uint32_t sync_ctrl;
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/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
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uint32_t raster_order;
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/* DMA FIFO threshold */
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uint32_t fifo_th;
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};
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#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev);
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irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
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void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
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void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
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const struct tilcdc_panel_info *info);
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void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
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bool simulate_vesa_sync);
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int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
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int tilcdc_crtc_max_width(struct drm_crtc *crtc);
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void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
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#endif /* __TILCDC_DRV_H__ */
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