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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9b081e1080
Today powerpc64 uses a set of pgtable_caches while powerpc32 uses standard pages when using 4k pages and a single pgtable_cache if using other size pages. In preparation of implementing huge pages on the 8xx, this patch replaces the specific powerpc32 handling by the 64 bits approach. This is done by: * moving 64 bits pgtable_cache_add() and pgtable_cache_init() in a new file called init-common.c * modifying pgtable_cache_init() to also handle the case without PMD * removing the 32 bits version of pgtable_cache_add() and pgtable_cache_init() * copying related header contents from 64 bits into both the book3s/32 and nohash/32 header files On the 8xx, the following cache sizes will be used: * 4k pages mode: - PGT_CACHE(10) for PGD - PGT_CACHE(3) for 512k hugepage tables * 16k pages mode: - PGT_CACHE(6) for PGD - PGT_CACHE(7) for 512k hugepage tables - PGT_CACHE(3) for 8M hugepage tables Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Scott Wood <oss@buserror.net>
86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_H
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#define _ASM_POWERPC_PGTABLE_H
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#ifndef __ASSEMBLY__
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#include <linux/mmdebug.h>
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#include <linux/mmzone.h>
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
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struct mm_struct;
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/book3s/pgtable.h>
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#else
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#include <asm/nohash/pgtable.h>
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#endif /* !CONFIG_PPC_BOOK3S */
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#ifndef __ASSEMBLY__
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#include <asm/tlbflush.h>
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/* Keep these as a macros to avoid include dependency mess */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
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int dma_pfn_limit_to_zone(u64 pfn_limit);
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extern void paging_init(void);
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/*
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* kern_addr_valid is intended to indicate whether an address is a valid
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* kernel address. Most 32-bit archs define it as always true (like this)
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* but most 64-bit archs actually perform a test. What should we do here?
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*/
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
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*/
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
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extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
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unsigned long end, int write,
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struct page **pages, int *nr);
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#ifndef CONFIG_TRANSPARENT_HUGEPAGE
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#define pmd_large(pmd) 0
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#endif
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pte_t *__find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
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bool *is_thp, unsigned *shift);
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static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
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bool *is_thp, unsigned *shift)
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{
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VM_WARN(!arch_irqs_disabled(),
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"%s called with irq enabled\n", __func__);
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return __find_linux_pte_or_hugepte(pgdir, ea, is_thp, shift);
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}
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unsigned long vmalloc_to_phys(void *vmalloc_addr);
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void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
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void pgtable_cache_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_H */
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