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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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15f6ddc7d9
The initial user manuals for MPC8544/8533 had some issues with properly documenting the device IDs for MPC8544/8533. These processors are almost identical and both show up on the reference boards. Fix up the quirks for PCIe support to handle MPC8533/E. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
260 lines
8.5 KiB
C
260 lines
8.5 KiB
C
/*
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* MPC85xx/86xx PCI/PCIE support routing.
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*
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* Copyright 2007 Freescale Semiconductor, Inc
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*
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Rewrite the routing for Frescale PCI and PCI Express
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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/* atmu setup for fsl pci/pcie controller */
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void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
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{
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struct ccsr_pci __iomem *pci;
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int i;
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pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
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rsrc->end - rsrc->start + 1);
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pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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/* Disable all windows (except powar0 since its ignored) */
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for(i = 1; i < 5; i++)
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out_be32(&pci->pow[i].powar, 0);
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for(i = 0; i < 3; i++)
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out_be32(&pci->piw[i].piwar, 0);
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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out_be32(&pci->pow[i+1].potar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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/* Enable, Mem R/W */
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out_be32(&pci->pow[i+1].powar, 0x80044000
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| (__ilog2(hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1) - 1));
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
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& 0x000fffff);
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
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& 0x000fffff);
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/* Enable, IO R/W */
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out_be32(&pci->pow[i+1].powar, 0x80088000
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| (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1));
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}
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/* Setup 2G inbound Memory Window @ 1 */
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out_be32(&pci->piw[2].pitar, 0x00000000);
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out_be32(&pci->piw[2].piwbar,0x00000000);
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out_be32(&pci->piw[2].piwar, PIWAR_2G);
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}
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void __init setup_pci_cmd(struct pci_controller *hose)
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{
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u16 cmd;
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int cap_x;
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
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cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
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if (cap_x) {
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int pci_x_cmd = cap_x + PCI_X_CMD;
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cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
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} else {
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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}
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}
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static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev)
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{
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struct resource *res;
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int i, res_idx = PCI_BRIDGE_RESOURCES;
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struct pci_controller *hose;
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return ;
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/*
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* Make the bridge be transparent.
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*/
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dev->transparent = 1;
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hose = pci_bus_to_host(dev->bus);
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if (!hose) {
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printk(KERN_ERR "Can't find hose for bus %d\n",
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dev->bus->number);
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return;
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}
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/* Clear out any of the virtual P2P bridge registers */
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
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pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
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pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
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pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
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pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
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pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
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pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
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pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
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if (hose->io_resource.flags) {
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res = &dev->resource[res_idx++];
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res->start = hose->io_resource.start;
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res->end = hose->io_resource.end;
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res->flags = hose->io_resource.flags;
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update_bridge_resource(dev, res);
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}
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for (i = 0; i < 3; i++) {
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res = &dev->resource[res_idx + i];
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res->start = hose->mem_resources[i].start;
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res->end = hose->mem_resources[i].end;
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res->flags = hose->mem_resources[i].flags;
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update_bridge_resource(dev, res);
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}
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}
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int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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u16 val;
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early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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void fsl_pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
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int i;
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/* deal with bogus pci_bus when we don't have anything connected on PCIe */
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
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if (bus->parent) {
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for (i = 0; i < 4; ++i)
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bus->resource[i] = bus->parent->resource[i];
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}
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}
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}
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int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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if (of_address_to_resource(dev, 0, &rsrc)) {
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printk(KERN_WARNING "Can't get pci register base!");
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return -ENOMEM;
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}
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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pci_assign_all_buses = 1;
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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setup_pci_cmd(hose);
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/* check PCI express link status */
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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}
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
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"Firmware bus number: %d->%d\n",
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(unsigned long long)rsrc.start, hose->first_busno,
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hose->last_busno);
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pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, is_primary);
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/* Setup PEX window registers */
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setup_pci_atmu(hose, &rsrc);
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return 0;
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent);
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