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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
232 lines
6.7 KiB
C
232 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2013, NVIDIA Corporation.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef __hw_host1x01_sync_h__
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#define __hw_host1x01_sync_h__
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#define REGISTER_STRIDE 4
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static inline u32 host1x_sync_syncpt_r(unsigned int id)
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{
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return 0x400 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT(id) \
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host1x_sync_syncpt_r(id)
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static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
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{
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return 0x40 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
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host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
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static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
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{
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return 0x60 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
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host1x_sync_syncpt_thresh_int_disable_r(id)
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static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
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{
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return 0x68 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
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host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
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static inline u32 host1x_sync_cf_setup_r(unsigned int channel)
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{
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return 0x80 + channel * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_CF_SETUP(channel) \
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host1x_sync_cf_setup_r(channel)
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static inline u32 host1x_sync_cf_setup_base_v(u32 r)
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{
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return (r >> 0) & 0x1ff;
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}
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#define HOST1X_SYNC_CF_SETUP_BASE_V(r) \
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host1x_sync_cf_setup_base_v(r)
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static inline u32 host1x_sync_cf_setup_limit_v(u32 r)
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{
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return (r >> 16) & 0x1ff;
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}
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#define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \
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host1x_sync_cf_setup_limit_v(r)
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static inline u32 host1x_sync_cmdproc_stop_r(void)
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{
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return 0xac;
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}
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#define HOST1X_SYNC_CMDPROC_STOP \
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host1x_sync_cmdproc_stop_r()
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static inline u32 host1x_sync_ch_teardown_r(void)
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{
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return 0xb0;
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}
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#define HOST1X_SYNC_CH_TEARDOWN \
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host1x_sync_ch_teardown_r()
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static inline u32 host1x_sync_usec_clk_r(void)
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{
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return 0x1a4;
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}
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#define HOST1X_SYNC_USEC_CLK \
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host1x_sync_usec_clk_r()
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static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
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{
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return 0x1a8;
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}
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#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
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host1x_sync_ctxsw_timeout_cfg_r()
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static inline u32 host1x_sync_ip_busy_timeout_r(void)
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{
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return 0x1bc;
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}
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#define HOST1X_SYNC_IP_BUSY_TIMEOUT \
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host1x_sync_ip_busy_timeout_r()
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static inline u32 host1x_sync_mlock_owner_r(unsigned int id)
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{
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return 0x340 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_MLOCK_OWNER(id) \
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host1x_sync_mlock_owner_r(id)
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static inline u32 host1x_sync_mlock_owner_chid_v(u32 v)
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{
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return (v >> 8) & 0xf;
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}
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#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
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host1x_sync_mlock_owner_chid_v(v)
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static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r)
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{
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return (r >> 1) & 0x1;
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}
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#define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \
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host1x_sync_mlock_owner_cpu_owns_v(r)
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static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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#define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \
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host1x_sync_mlock_owner_ch_owns_v(r)
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static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
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{
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return 0x500 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
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host1x_sync_syncpt_int_thresh_r(id)
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static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
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{
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return 0x600 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_BASE(id) \
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host1x_sync_syncpt_base_r(id)
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static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
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{
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return 0x700 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
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host1x_sync_syncpt_cpu_incr_r(id)
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static inline u32 host1x_sync_cbread_r(unsigned int channel)
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{
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return 0x720 + channel * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_CBREAD(channel) \
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host1x_sync_cbread_r(channel)
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static inline u32 host1x_sync_cfpeek_ctrl_r(void)
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{
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return 0x74c;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL \
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host1x_sync_cfpeek_ctrl_r()
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static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
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{
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return (v & 0x1ff) << 0;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
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host1x_sync_cfpeek_ctrl_addr_f(v)
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static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
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{
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return (v & 0x7) << 16;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
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host1x_sync_cfpeek_ctrl_channr_f(v)
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static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
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{
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return (v & 0x1) << 31;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
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host1x_sync_cfpeek_ctrl_ena_f(v)
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static inline u32 host1x_sync_cfpeek_read_r(void)
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{
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return 0x750;
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}
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#define HOST1X_SYNC_CFPEEK_READ \
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host1x_sync_cfpeek_read_r()
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static inline u32 host1x_sync_cfpeek_ptrs_r(void)
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{
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return 0x754;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS \
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host1x_sync_cfpeek_ptrs_r()
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static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
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{
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return (r >> 0) & 0x1ff;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \
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host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r)
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static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
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{
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return (r >> 16) & 0x1ff;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \
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host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r)
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static inline u32 host1x_sync_cbstat_r(unsigned int channel)
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{
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return 0x758 + channel * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_CBSTAT(channel) \
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host1x_sync_cbstat_r(channel)
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static inline u32 host1x_sync_cbstat_cboffset_v(u32 r)
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{
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return (r >> 0) & 0xffff;
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}
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#define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \
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host1x_sync_cbstat_cboffset_v(r)
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static inline u32 host1x_sync_cbstat_cbclass_v(u32 r)
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{
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return (r >> 16) & 0x3ff;
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}
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#define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \
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host1x_sync_cbstat_cbclass_v(r)
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#endif /* __hw_host1x01_sync_h__ */
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