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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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662af0d822
This patch adds ARGB hardware cursor support to the DRM driver for the Marvell Armada SoCs. ARGB cursors are supported at either 32x64 or 64x32 resolutions. Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
319 lines
8.5 KiB
C
319 lines
8.5 KiB
C
/*
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* Copyright (C) 2012 Russell King
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* Rewritten from the dovefb driver, and Armada510 manuals.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ARMADA_HW_H
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#define ARMADA_HW_H
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/*
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* Note: the following registers are written from IRQ context:
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* LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
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* LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC,
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* LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN,
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* LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0
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*/
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enum {
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LCD_SPU_ADV_REG = 0x0084, /* Armada 510 */
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LCD_SPU_DMA_START_ADDR_Y0 = 0x00c0,
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LCD_SPU_DMA_START_ADDR_U0 = 0x00c4,
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LCD_SPU_DMA_START_ADDR_V0 = 0x00c8,
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LCD_CFG_DMA_START_ADDR_0 = 0x00cc,
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LCD_SPU_DMA_START_ADDR_Y1 = 0x00d0,
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LCD_SPU_DMA_START_ADDR_U1 = 0x00d4,
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LCD_SPU_DMA_START_ADDR_V1 = 0x00d8,
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LCD_CFG_DMA_START_ADDR_1 = 0x00dc,
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LCD_SPU_DMA_PITCH_YC = 0x00e0,
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LCD_SPU_DMA_PITCH_UV = 0x00e4,
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LCD_SPU_DMA_OVSA_HPXL_VLN = 0x00e8,
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LCD_SPU_DMA_HPXL_VLN = 0x00ec,
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LCD_SPU_DZM_HPXL_VLN = 0x00f0,
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LCD_CFG_GRA_START_ADDR0 = 0x00f4,
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LCD_CFG_GRA_START_ADDR1 = 0x00f8,
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LCD_CFG_GRA_PITCH = 0x00fc,
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LCD_SPU_GRA_OVSA_HPXL_VLN = 0x0100,
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LCD_SPU_GRA_HPXL_VLN = 0x0104,
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LCD_SPU_GZM_HPXL_VLN = 0x0108,
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LCD_SPU_HWC_OVSA_HPXL_VLN = 0x010c,
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LCD_SPU_HWC_HPXL_VLN = 0x0110,
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LCD_SPUT_V_H_TOTAL = 0x0114,
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LCD_SPU_V_H_ACTIVE = 0x0118,
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LCD_SPU_H_PORCH = 0x011c,
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LCD_SPU_V_PORCH = 0x0120,
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LCD_SPU_BLANKCOLOR = 0x0124,
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LCD_SPU_ALPHA_COLOR1 = 0x0128,
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LCD_SPU_ALPHA_COLOR2 = 0x012c,
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LCD_SPU_COLORKEY_Y = 0x0130,
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LCD_SPU_COLORKEY_U = 0x0134,
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LCD_SPU_COLORKEY_V = 0x0138,
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LCD_CFG_RDREG4F = 0x013c, /* Armada 510 */
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LCD_SPU_SPI_RXDATA = 0x0140,
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LCD_SPU_ISA_RXDATA = 0x0144,
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LCD_SPU_HWC_RDDAT = 0x0158,
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LCD_SPU_GAMMA_RDDAT = 0x015c,
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LCD_SPU_PALETTE_RDDAT = 0x0160,
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LCD_SPU_IOPAD_IN = 0x0178,
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LCD_CFG_RDREG5F = 0x017c,
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LCD_SPU_SPI_CTRL = 0x0180,
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LCD_SPU_SPI_TXDATA = 0x0184,
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LCD_SPU_SMPN_CTRL = 0x0188,
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LCD_SPU_DMA_CTRL0 = 0x0190,
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LCD_SPU_DMA_CTRL1 = 0x0194,
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LCD_SPU_SRAM_CTRL = 0x0198,
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LCD_SPU_SRAM_WRDAT = 0x019c,
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LCD_SPU_SRAM_PARA0 = 0x01a0, /* Armada 510 */
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LCD_SPU_SRAM_PARA1 = 0x01a4,
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LCD_CFG_SCLK_DIV = 0x01a8,
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LCD_SPU_CONTRAST = 0x01ac,
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LCD_SPU_SATURATION = 0x01b0,
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LCD_SPU_CBSH_HUE = 0x01b4,
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LCD_SPU_DUMB_CTRL = 0x01b8,
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LCD_SPU_IOPAD_CONTROL = 0x01bc,
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LCD_SPU_IRQ_ENA = 0x01c0,
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LCD_SPU_IRQ_ISR = 0x01c4,
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};
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/* For LCD_SPU_ADV_REG */
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enum {
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ADV_VSYNC_L_OFF = 0xfff << 20,
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ADV_GRACOLORKEY = 1 << 19,
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ADV_VIDCOLORKEY = 1 << 18,
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ADV_HWC32BLEND = 1 << 15,
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ADV_HWC32ARGB = 1 << 14,
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ADV_HWC32ENABLE = 1 << 13,
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ADV_VSYNCOFFEN = 1 << 12,
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ADV_VSYNC_H_OFF = 0xfff << 0,
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};
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enum {
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CFG_565 = 0,
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CFG_1555 = 1,
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CFG_888PACK = 2,
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CFG_X888 = 3,
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CFG_8888 = 4,
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CFG_422PACK = 5,
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CFG_422 = 6,
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CFG_420 = 7,
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CFG_PSEUDO4 = 9,
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CFG_PSEUDO8 = 10,
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CFG_SWAPRB = 1 << 4,
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CFG_SWAPUV = 1 << 3,
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CFG_SWAPYU = 1 << 2,
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CFG_YUV2RGB = 1 << 1,
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};
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/* For LCD_SPU_DMA_CTRL0 */
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enum {
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CFG_NOBLENDING = 1 << 31,
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CFG_GAMMA_ENA = 1 << 30,
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CFG_CBSH_ENA = 1 << 29,
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CFG_PALETTE_ENA = 1 << 28,
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CFG_ARBFAST_ENA = 1 << 27,
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CFG_HWC_1BITMOD = 1 << 26,
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CFG_HWC_1BITENA = 1 << 25,
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CFG_HWC_ENA = 1 << 24,
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CFG_DMAFORMAT = 0xf << 20,
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#define CFG_DMA_FMT(x) ((x) << 20)
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CFG_GRAFORMAT = 0xf << 16,
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#define CFG_GRA_FMT(x) ((x) << 16)
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#define CFG_GRA_MOD(x) ((x) << 8)
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CFG_GRA_FTOGGLE = 1 << 15,
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CFG_GRA_HSMOOTH = 1 << 14,
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CFG_GRA_TSTMODE = 1 << 13,
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CFG_GRA_ENA = 1 << 8,
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#define CFG_DMA_MOD(x) ((x) << 0)
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CFG_DMA_FTOGGLE = 1 << 7,
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CFG_DMA_HSMOOTH = 1 << 6,
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CFG_DMA_TSTMODE = 1 << 5,
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CFG_DMA_ENA = 1 << 0,
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};
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enum {
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CKMODE_DISABLE = 0,
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CKMODE_Y = 1,
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CKMODE_U = 2,
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CKMODE_RGB = 3,
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CKMODE_V = 4,
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CKMODE_R = 5,
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CKMODE_G = 6,
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CKMODE_B = 7,
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};
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/* For LCD_SPU_DMA_CTRL1 */
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enum {
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CFG_FRAME_TRIG = 1 << 31,
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CFG_VSYNC_INV = 1 << 27,
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CFG_CKMODE_MASK = 0x7 << 24,
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#define CFG_CKMODE(x) ((x) << 24)
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CFG_CARRY = 1 << 23,
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CFG_GATED_CLK = 1 << 21,
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CFG_PWRDN_ENA = 1 << 20,
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CFG_DSCALE_MASK = 0x3 << 18,
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CFG_DSCALE_NONE = 0x0 << 18,
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CFG_DSCALE_HALF = 0x1 << 18,
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CFG_DSCALE_QUAR = 0x2 << 18,
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CFG_ALPHAM_MASK = 0x3 << 16,
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CFG_ALPHAM_VIDEO = 0x0 << 16,
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CFG_ALPHAM_GRA = 0x1 << 16,
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CFG_ALPHAM_CFG = 0x2 << 16,
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CFG_ALPHA_MASK = 0xff << 8,
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CFG_PIXCMD_MASK = 0xff,
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};
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/* For LCD_SPU_SRAM_CTRL */
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enum {
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SRAM_READ = 0 << 14,
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SRAM_WRITE = 2 << 14,
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SRAM_INIT = 3 << 14,
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SRAM_HWC32_RAM1 = 0xc << 8,
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SRAM_HWC32_RAM2 = 0xd << 8,
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SRAM_HWC32_RAMR = SRAM_HWC32_RAM1,
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SRAM_HWC32_RAMG = SRAM_HWC32_RAM2,
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SRAM_HWC32_RAMB = 0xe << 8,
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SRAM_HWC32_TRAN = 0xf << 8,
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SRAM_HWC = 0xf << 8,
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};
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/* For LCD_SPU_SRAM_PARA1 */
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enum {
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CFG_CSB_256x32 = 1 << 15, /* cursor */
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CFG_CSB_256x24 = 1 << 14, /* palette */
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CFG_CSB_256x8 = 1 << 13, /* gamma */
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CFG_PDWN1920x32 = 1 << 8, /* Armada 510: power down vscale ram */
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CFG_PDWN256x32 = 1 << 7, /* power down cursor */
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CFG_PDWN256x24 = 1 << 6, /* power down palette */
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CFG_PDWN256x8 = 1 << 5, /* power down gamma */
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CFG_PDWNHWC = 1 << 4, /* Armada 510: power down all hwc ram */
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CFG_PDWN32x32 = 1 << 3, /* power down slave->smart ram */
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CFG_PDWN16x66 = 1 << 2, /* power down UV fifo */
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CFG_PDWN32x66 = 1 << 1, /* power down Y fifo */
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CFG_PDWN64x66 = 1 << 0, /* power down graphic fifo */
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};
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/* For LCD_CFG_SCLK_DIV */
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enum {
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/* Armada 510 */
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SCLK_510_AXI = 0x0 << 30,
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SCLK_510_EXTCLK0 = 0x1 << 30,
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SCLK_510_PLL = 0x2 << 30,
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SCLK_510_EXTCLK1 = 0x3 << 30,
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SCLK_510_DIV_CHANGE = 1 << 29,
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SCLK_510_FRAC_DIV_MASK = 0xfff << 16,
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SCLK_510_INT_DIV_MASK = 0xffff << 0,
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/* Armada 16x */
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SCLK_16X_AHB = 0x0 << 28,
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SCLK_16X_PCLK = 0x1 << 28,
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SCLK_16X_AXI = 0x4 << 28,
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SCLK_16X_PLL = 0x8 << 28,
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SCLK_16X_FRAC_DIV_MASK = 0xfff << 16,
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SCLK_16X_INT_DIV_MASK = 0xffff << 0,
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};
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/* For LCD_SPU_DUMB_CTRL */
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enum {
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DUMB16_RGB565_0 = 0x0 << 28,
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DUMB16_RGB565_1 = 0x1 << 28,
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DUMB18_RGB666_0 = 0x2 << 28,
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DUMB18_RGB666_1 = 0x3 << 28,
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DUMB12_RGB444_0 = 0x4 << 28,
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DUMB12_RGB444_1 = 0x5 << 28,
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DUMB24_RGB888_0 = 0x6 << 28,
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DUMB_BLANK = 0x7 << 28,
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DUMB_MASK = 0xf << 28,
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CFG_BIAS_OUT = 1 << 8,
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CFG_REV_RGB = 1 << 7,
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CFG_INV_CBLANK = 1 << 6,
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CFG_INV_CSYNC = 1 << 5, /* Normally active high */
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CFG_INV_HENA = 1 << 4,
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CFG_INV_VSYNC = 1 << 3, /* Normally active high */
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CFG_INV_HSYNC = 1 << 2, /* Normally active high */
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CFG_INV_PCLK = 1 << 1,
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CFG_DUMB_ENA = 1 << 0,
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};
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/* For LCD_SPU_IOPAD_CONTROL */
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enum {
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CFG_VSCALE_LN_EN = 3 << 18,
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CFG_GRA_VM_ENA = 1 << 15,
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CFG_DMA_VM_ENA = 1 << 13,
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CFG_CMD_VM_ENA = 1 << 11,
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CFG_CSC_MASK = 3 << 8,
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CFG_CSC_YUV_CCIR709 = 1 << 9,
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CFG_CSC_YUV_CCIR601 = 0 << 9,
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CFG_CSC_RGB_STUDIO = 1 << 8,
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CFG_CSC_RGB_COMPUTER = 0 << 8,
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CFG_IOPAD_MASK = 0xf << 0,
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CFG_IOPAD_DUMB24 = 0x0 << 0,
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CFG_IOPAD_DUMB18SPI = 0x1 << 0,
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CFG_IOPAD_DUMB18GPIO = 0x2 << 0,
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CFG_IOPAD_DUMB16SPI = 0x3 << 0,
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CFG_IOPAD_DUMB16GPIO = 0x4 << 0,
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CFG_IOPAD_DUMB12GPIO = 0x5 << 0,
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CFG_IOPAD_SMART18 = 0x6 << 0,
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CFG_IOPAD_SMART16 = 0x7 << 0,
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CFG_IOPAD_SMART8 = 0x8 << 0,
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};
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#define IOPAD_DUMB24 0x0
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/* For LCD_SPU_IRQ_ENA */
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enum {
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DMA_FRAME_IRQ0_ENA = 1 << 31,
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DMA_FRAME_IRQ1_ENA = 1 << 30,
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DMA_FRAME_IRQ_ENA = DMA_FRAME_IRQ0_ENA | DMA_FRAME_IRQ1_ENA,
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DMA_FF_UNDERFLOW_ENA = 1 << 29,
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GRA_FRAME_IRQ0_ENA = 1 << 27,
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GRA_FRAME_IRQ1_ENA = 1 << 26,
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GRA_FRAME_IRQ_ENA = GRA_FRAME_IRQ0_ENA | GRA_FRAME_IRQ1_ENA,
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GRA_FF_UNDERFLOW_ENA = 1 << 25,
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VSYNC_IRQ_ENA = 1 << 23,
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DUMB_FRAMEDONE_ENA = 1 << 22,
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TWC_FRAMEDONE_ENA = 1 << 21,
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HWC_FRAMEDONE_ENA = 1 << 20,
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SLV_IRQ_ENA = 1 << 19,
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SPI_IRQ_ENA = 1 << 18,
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PWRDN_IRQ_ENA = 1 << 17,
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ERR_IRQ_ENA = 1 << 16,
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CLEAN_SPU_IRQ_ISR = 0xffff,
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};
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/* For LCD_SPU_IRQ_ISR */
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enum {
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DMA_FRAME_IRQ0 = 1 << 31,
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DMA_FRAME_IRQ1 = 1 << 30,
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DMA_FRAME_IRQ = DMA_FRAME_IRQ0 | DMA_FRAME_IRQ1,
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DMA_FF_UNDERFLOW = 1 << 29,
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GRA_FRAME_IRQ0 = 1 << 27,
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GRA_FRAME_IRQ1 = 1 << 26,
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GRA_FRAME_IRQ = GRA_FRAME_IRQ0 | GRA_FRAME_IRQ1,
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GRA_FF_UNDERFLOW = 1 << 25,
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VSYNC_IRQ = 1 << 23,
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DUMB_FRAMEDONE = 1 << 22,
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TWC_FRAMEDONE = 1 << 21,
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HWC_FRAMEDONE = 1 << 20,
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SLV_IRQ = 1 << 19,
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SPI_IRQ = 1 << 18,
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PWRDN_IRQ = 1 << 17,
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ERR_IRQ = 1 << 16,
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DMA_FRAME_IRQ0_LEVEL = 1 << 15,
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DMA_FRAME_IRQ1_LEVEL = 1 << 14,
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DMA_FRAME_CNT_ISR = 3 << 12,
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GRA_FRAME_IRQ0_LEVEL = 1 << 11,
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GRA_FRAME_IRQ1_LEVEL = 1 << 10,
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GRA_FRAME_CNT_ISR = 3 << 8,
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VSYNC_IRQ_LEVEL = 1 << 7,
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DUMB_FRAMEDONE_LEVEL = 1 << 6,
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TWC_FRAMEDONE_LEVEL = 1 << 5,
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HWC_FRAMEDONE_LEVEL = 1 << 4,
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SLV_FF_EMPTY = 1 << 3,
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DMA_FF_ALLEMPTY = 1 << 2,
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GRA_FF_ALLEMPTY = 1 << 1,
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PWRDN_IRQ_LEVEL = 1 << 0,
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};
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#endif
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