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0ccdacf694
Allow for the MOCS to be programmed for all engines. Currently we program the MOCS when the first render batch goes through. This works on most platforms but fails on platforms that do not run a render batch early, i.e. headless servers. The patch now programs all initialised engines on init and the RCS is programmed again within the initial batch. This is done for predictable consistency with regards to the hardware context. Hardware context loading sets the values of the MOCS for RCS and L3CC. Programming them from within the batch makes sure that the render context is valid, no matter what the previous state of the saved-context was. v2: posted correct version to the mailing list. v3: moved programming to within engine->init_hw() (Chris Wilson) v4: code formatting and white-space changes. (Chris Wilson) Testcase: igt/gem_mocs_settings Signed-off-by: Peter Antoine <peter.antoine@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1460556205-6644-1-git-send-email-chris@chris-wilson.co.uk
60 lines
2.3 KiB
C
60 lines
2.3 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef INTEL_MOCS_H
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#define INTEL_MOCS_H
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/**
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* DOC: Memory Objects Control State (MOCS)
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*
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* Motivation:
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* In previous Gens the MOCS settings was a value that was set by user land as
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* part of the batch. In Gen9 this has changed to be a single table (per ring)
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* that all batches now reference by index instead of programming the MOCS
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* directly.
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*
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* The one wrinkle in this is that only PART of the MOCS tables are included
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* in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32
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* registers). The rest are not (the settings for the other rings).
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*
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* This table needs to be set at system start-up because the way the table
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* interacts with the contexts and the GmmLib interface.
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*
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*
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* Implementation:
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*
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* The tables (one per supported platform) are defined in intel_mocs.c
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* and are programmed in the first batch after the context is loaded
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* (with the hardware workarounds). This will then let the usual
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* context handling keep the MOCS in step.
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*/
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#include <drm/drmP.h>
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#include "i915_drv.h"
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int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req);
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void intel_mocs_init_l3cc_table(struct drm_device *dev);
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int intel_mocs_init_engine(struct intel_engine_cs *ring);
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#endif
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