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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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be8454afc5
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdLMSbAAoJEAx081l5xIa+udkP/iWr8mw44tWYb8Wuzc/aR91v 02X/J4S9XTQttNn/1Gpq9ItTLMf0Gc08tk1wEBBHAWi/qGaGZS2al+rv0afeuuQa aFhQzioDi7K/YZt92iEJhdx7wVMyydICTg3INmYlSP7/FyzLp6gBQRGSJ1kX5mHZ qWsFZgUOH9V5evyB6fDMleDaqFOKfcwrD7XYwbOheL/HeYQSv5AYn3VBupBFQ76L 0hclI5VzZQ5V0nnqRTNDQVA9Yl6NTl+2eXTn5vuBtwKXEI6JJw8eihZp2oZDXqfS L441w7wGbkRPzN5kjMZjs1ToPMTlMveR5kL6Sc+o3DT/HmIr1odeaSDXR/93UOLd z0CRJ6xMC8h1ThLNHp8UgbxCKqIwYPsY2wVqjsJt7lDY5jma7Yv2YJ9ocYGHN/sO DVHcU6ugbwvuC5wZZtVZl5J4hjnBZwNRGSVK+iM0tkjalgdEuSFehXT7eQ8SphF/ yI5gD1xNEwGfZ4bvZ3u/QrDCcpUAgPIUYmxEa2tPJILQWOJ9O87yc0y9Z21k9Ef1 9yDqrFV3sPqC2xj/0ufZG/18+Yt99Ykg1jQE3RGDwD/59KAeqPbOvqTKyVODV9jE qje6ScSIc2G0713uss2bcaD3k+rCB5YL2JkKrk5OWW/T2+n9T+JFaiNh7dnSFFcU gBKyeY24OyCDMwXrby0K =SI+Y -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
847 lines
24 KiB
C
847 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2019 Intel Corporation
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*
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* mei_hdcp.c: HDCP client driver for mei bus
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*
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* Author:
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* Ramalingam C <ramalingam.c@intel.com>
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*/
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/**
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* DOC: MEI_HDCP Client Driver
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*
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* The mei_hdcp driver acts as a translation layer between HDCP 2.2
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* protocol implementer (I915) and ME FW by translating HDCP2.2
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* negotiation messages to ME FW command payloads and vice versa.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/uuid.h>
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#include <linux/mei_cl_bus.h>
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#include <linux/component.h>
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#include <drm/drm_connector.h>
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#include <drm/i915_component.h>
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#include <drm/i915_mei_hdcp_interface.h>
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#include "mei_hdcp.h"
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static inline u8 mei_get_ddi_index(enum port port)
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{
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switch (port) {
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case PORT_A:
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return MEI_DDI_A;
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case PORT_B ... PORT_F:
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return (u8)port;
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default:
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return MEI_DDI_INVALID_PORT;
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}
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}
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/**
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* mei_hdcp_initiate_session() - Initiate a Wired HDCP2.2 Tx Session in ME FW
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* @dev: device corresponding to the mei_cl_device
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* @data: Intel HW specific hdcp data
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* @ake_data: AKE_Init msg output.
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*
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* Return: 0 on Success, <0 on Failure.
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*/
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static int
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mei_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
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struct hdcp2_ake_init *ake_data)
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{
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struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
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struct wired_cmd_initiate_hdcp2_session_out
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session_init_out = { { 0 } };
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struct mei_cl_device *cldev;
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ssize_t byte;
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if (!dev || !data || !ake_data)
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return -EINVAL;
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cldev = to_mei_cl_device(dev);
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session_init_in.header.api_version = HDCP_API_VERSION;
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session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
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session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
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session_init_in.header.buffer_len =
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WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
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session_init_in.port.integrated_port_type = data->port_type;
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session_init_in.port.physical_port = mei_get_ddi_index(data->port);
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session_init_in.protocol = data->protocol;
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byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
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sizeof(session_init_in));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
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return byte;
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}
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byte = mei_cldev_recv(cldev, (u8 *)&session_init_out,
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sizeof(session_init_out));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
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return byte;
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}
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if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
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dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
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WIRED_INITIATE_HDCP2_SESSION,
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session_init_out.header.status);
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return -EIO;
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}
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ake_data->msg_id = HDCP_2_2_AKE_INIT;
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ake_data->tx_caps = session_init_out.tx_caps;
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memcpy(ake_data->r_tx, session_init_out.r_tx, HDCP_2_2_RTX_LEN);
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return 0;
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}
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/**
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* mei_hdcp_verify_receiver_cert_prepare_km() - Verify the Receiver Certificate
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* AKE_Send_Cert and prepare AKE_Stored_Km/AKE_No_Stored_Km
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* @dev: device corresponding to the mei_cl_device
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* @data: Intel HW specific hdcp data
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* @rx_cert: AKE_Send_Cert for verification
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* @km_stored: Pairing status flag output
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* @ek_pub_km: AKE_Stored_Km/AKE_No_Stored_Km output msg
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* @msg_sz : size of AKE_XXXXX_Km output msg
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*
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* Return: 0 on Success, <0 on Failure
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*/
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static int
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mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
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struct hdcp_port_data *data,
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struct hdcp2_ake_send_cert *rx_cert,
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bool *km_stored,
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struct hdcp2_ake_no_stored_km
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*ek_pub_km,
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size_t *msg_sz)
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{
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struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } };
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struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } };
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struct mei_cl_device *cldev;
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ssize_t byte;
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if (!dev || !data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz)
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return -EINVAL;
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cldev = to_mei_cl_device(dev);
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verify_rxcert_in.header.api_version = HDCP_API_VERSION;
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verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
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verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
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verify_rxcert_in.header.buffer_len =
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WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
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verify_rxcert_in.port.integrated_port_type = data->port_type;
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verify_rxcert_in.port.physical_port = mei_get_ddi_index(data->port);
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verify_rxcert_in.cert_rx = rx_cert->cert_rx;
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memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
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memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN);
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byte = mei_cldev_send(cldev, (u8 *)&verify_rxcert_in,
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sizeof(verify_rxcert_in));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_send failed: %zd\n", byte);
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return byte;
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}
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byte = mei_cldev_recv(cldev, (u8 *)&verify_rxcert_out,
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sizeof(verify_rxcert_out));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_recv failed: %zd\n", byte);
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return byte;
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}
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if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
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dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
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WIRED_VERIFY_RECEIVER_CERT,
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verify_rxcert_out.header.status);
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return -EIO;
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}
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*km_stored = !!verify_rxcert_out.km_stored;
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if (verify_rxcert_out.km_stored) {
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ek_pub_km->msg_id = HDCP_2_2_AKE_STORED_KM;
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*msg_sz = sizeof(struct hdcp2_ake_stored_km);
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} else {
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ek_pub_km->msg_id = HDCP_2_2_AKE_NO_STORED_KM;
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*msg_sz = sizeof(struct hdcp2_ake_no_stored_km);
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}
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memcpy(ek_pub_km->e_kpub_km, &verify_rxcert_out.ekm_buff,
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sizeof(verify_rxcert_out.ekm_buff));
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return 0;
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}
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/**
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* mei_hdcp_verify_hprime() - Verify AKE_Send_H_prime at ME FW.
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* @dev: device corresponding to the mei_cl_device
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* @data: Intel HW specific hdcp data
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* @rx_hprime: AKE_Send_H_prime msg for ME FW verification
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*
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* Return: 0 on Success, <0 on Failure
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*/
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static int
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mei_hdcp_verify_hprime(struct device *dev, struct hdcp_port_data *data,
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struct hdcp2_ake_send_hprime *rx_hprime)
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{
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struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } };
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struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } };
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struct mei_cl_device *cldev;
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ssize_t byte;
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if (!dev || !data || !rx_hprime)
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return -EINVAL;
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cldev = to_mei_cl_device(dev);
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send_hprime_in.header.api_version = HDCP_API_VERSION;
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send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
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send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
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send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
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send_hprime_in.port.integrated_port_type = data->port_type;
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send_hprime_in.port.physical_port = mei_get_ddi_index(data->port);
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memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
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HDCP_2_2_H_PRIME_LEN);
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byte = mei_cldev_send(cldev, (u8 *)&send_hprime_in,
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sizeof(send_hprime_in));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
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return byte;
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}
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byte = mei_cldev_recv(cldev, (u8 *)&send_hprime_out,
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sizeof(send_hprime_out));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
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return byte;
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}
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if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
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dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
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WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
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return -EIO;
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}
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return 0;
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}
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/**
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* mei_hdcp_store_pairing_info() - Store pairing info received at ME FW
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* @dev: device corresponding to the mei_cl_device
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* @data: Intel HW specific hdcp data
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* @pairing_info: AKE_Send_Pairing_Info msg input to ME FW
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*
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* Return: 0 on Success, <0 on Failure
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*/
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static int
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mei_hdcp_store_pairing_info(struct device *dev, struct hdcp_port_data *data,
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struct hdcp2_ake_send_pairing_info *pairing_info)
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{
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struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } };
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struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } };
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struct mei_cl_device *cldev;
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ssize_t byte;
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if (!dev || !data || !pairing_info)
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return -EINVAL;
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cldev = to_mei_cl_device(dev);
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pairing_info_in.header.api_version = HDCP_API_VERSION;
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pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
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pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
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pairing_info_in.header.buffer_len =
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WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
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pairing_info_in.port.integrated_port_type = data->port_type;
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pairing_info_in.port.physical_port = mei_get_ddi_index(data->port);
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memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
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HDCP_2_2_E_KH_KM_LEN);
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byte = mei_cldev_send(cldev, (u8 *)&pairing_info_in,
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sizeof(pairing_info_in));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
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return byte;
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}
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byte = mei_cldev_recv(cldev, (u8 *)&pairing_info_out,
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sizeof(pairing_info_out));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
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return byte;
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}
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if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
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dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",
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WIRED_AKE_SEND_PAIRING_INFO,
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pairing_info_out.header.status);
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return -EIO;
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}
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return 0;
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}
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/**
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* mei_hdcp_initiate_locality_check() - Prepare LC_Init
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* @dev: device corresponding to the mei_cl_device
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* @data: Intel HW specific hdcp data
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* @lc_init_data: LC_Init msg output
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*
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* Return: 0 on Success, <0 on Failure
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*/
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static int
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mei_hdcp_initiate_locality_check(struct device *dev,
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struct hdcp_port_data *data,
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struct hdcp2_lc_init *lc_init_data)
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{
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struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } };
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struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } };
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struct mei_cl_device *cldev;
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ssize_t byte;
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if (!dev || !data || !lc_init_data)
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return -EINVAL;
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cldev = to_mei_cl_device(dev);
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lc_init_in.header.api_version = HDCP_API_VERSION;
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lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
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lc_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
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lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
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lc_init_in.port.integrated_port_type = data->port_type;
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lc_init_in.port.physical_port = mei_get_ddi_index(data->port);
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byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
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return byte;
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}
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byte = mei_cldev_recv(cldev, (u8 *)&lc_init_out, sizeof(lc_init_out));
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if (byte < 0) {
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dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
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return byte;
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}
|
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|
|
if (lc_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X Failed. status: 0x%X\n",
|
|
WIRED_INIT_LOCALITY_CHECK, lc_init_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
lc_init_data->msg_id = HDCP_2_2_LC_INIT;
|
|
memcpy(lc_init_data->r_n, lc_init_out.r_n, HDCP_2_2_RN_LEN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_verify_lprime() - Verify lprime.
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
* @rx_lprime: LC_Send_L_prime msg for ME FW verification
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int
|
|
mei_hdcp_verify_lprime(struct device *dev, struct hdcp_port_data *data,
|
|
struct hdcp2_lc_send_lprime *rx_lprime)
|
|
{
|
|
struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } };
|
|
struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !data || !rx_lprime)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
verify_lprime_in.header.api_version = HDCP_API_VERSION;
|
|
verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY;
|
|
verify_lprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
verify_lprime_in.header.buffer_len =
|
|
WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
|
|
|
|
verify_lprime_in.port.integrated_port_type = data->port_type;
|
|
verify_lprime_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
|
|
memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
|
|
HDCP_2_2_L_PRIME_LEN);
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&verify_lprime_in,
|
|
sizeof(verify_lprime_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&verify_lprime_out,
|
|
sizeof(verify_lprime_out));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (verify_lprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
|
|
WIRED_VALIDATE_LOCALITY,
|
|
verify_lprime_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_get_session_key() - Prepare SKE_Send_Eks.
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
* @ske_data: SKE_Send_Eks msg output from ME FW.
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int mei_hdcp_get_session_key(struct device *dev,
|
|
struct hdcp_port_data *data,
|
|
struct hdcp2_ske_send_eks *ske_data)
|
|
{
|
|
struct wired_cmd_get_session_key_in get_skey_in = { { 0 } };
|
|
struct wired_cmd_get_session_key_out get_skey_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !data || !ske_data)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
get_skey_in.header.api_version = HDCP_API_VERSION;
|
|
get_skey_in.header.command_id = WIRED_GET_SESSION_KEY;
|
|
get_skey_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
|
|
|
|
get_skey_in.port.integrated_port_type = data->port_type;
|
|
get_skey_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&get_skey_out, sizeof(get_skey_out));
|
|
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (get_skey_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
|
|
WIRED_GET_SESSION_KEY, get_skey_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
ske_data->msg_id = HDCP_2_2_SKE_SEND_EKS;
|
|
memcpy(ske_data->e_dkey_ks, get_skey_out.e_dkey_ks,
|
|
HDCP_2_2_E_DKEY_KS_LEN);
|
|
memcpy(ske_data->riv, get_skey_out.r_iv, HDCP_2_2_RIV_LEN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_repeater_check_flow_prepare_ack() - Validate the Downstream topology
|
|
* and prepare rep_ack.
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
* @rep_topology: Receiver ID List to be validated
|
|
* @rep_send_ack : repeater ack from ME FW.
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int
|
|
mei_hdcp_repeater_check_flow_prepare_ack(struct device *dev,
|
|
struct hdcp_port_data *data,
|
|
struct hdcp2_rep_send_receiverid_list
|
|
*rep_topology,
|
|
struct hdcp2_rep_send_ack
|
|
*rep_send_ack)
|
|
{
|
|
struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } };
|
|
struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !rep_topology || !rep_send_ack || !data)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
verify_repeater_in.header.api_version = HDCP_API_VERSION;
|
|
verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER;
|
|
verify_repeater_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
verify_repeater_in.header.buffer_len =
|
|
WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
|
|
|
|
verify_repeater_in.port.integrated_port_type = data->port_type;
|
|
verify_repeater_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
|
|
memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
|
|
HDCP_2_2_RXINFO_LEN);
|
|
memcpy(verify_repeater_in.seq_num_v, rep_topology->seq_num_v,
|
|
HDCP_2_2_SEQ_NUM_LEN);
|
|
memcpy(verify_repeater_in.v_prime, rep_topology->v_prime,
|
|
HDCP_2_2_V_PRIME_HALF_LEN);
|
|
memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids,
|
|
HDCP_2_2_RECEIVER_IDS_MAX_LEN);
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&verify_repeater_in,
|
|
sizeof(verify_repeater_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&verify_repeater_out,
|
|
sizeof(verify_repeater_out));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (verify_repeater_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
|
|
WIRED_VERIFY_REPEATER,
|
|
verify_repeater_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
memcpy(rep_send_ack->v, verify_repeater_out.v,
|
|
HDCP_2_2_V_PRIME_HALF_LEN);
|
|
rep_send_ack->msg_id = HDCP_2_2_REP_SEND_ACK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_verify_mprime() - Verify mprime.
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
* @stream_ready: RepeaterAuth_Stream_Ready msg for ME FW verification.
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int mei_hdcp_verify_mprime(struct device *dev,
|
|
struct hdcp_port_data *data,
|
|
struct hdcp2_rep_stream_ready *stream_ready)
|
|
{
|
|
struct wired_cmd_repeater_auth_stream_req_in
|
|
verify_mprime_in = { { 0 } };
|
|
struct wired_cmd_repeater_auth_stream_req_out
|
|
verify_mprime_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !stream_ready || !data)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
verify_mprime_in.header.api_version = HDCP_API_VERSION;
|
|
verify_mprime_in.header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
|
|
verify_mprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
verify_mprime_in.header.buffer_len =
|
|
WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
|
|
|
|
verify_mprime_in.port.integrated_port_type = data->port_type;
|
|
verify_mprime_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
|
|
memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
|
|
HDCP_2_2_MPRIME_LEN);
|
|
drm_hdcp_cpu_to_be24(verify_mprime_in.seq_num_m, data->seq_num_m);
|
|
memcpy(verify_mprime_in.streams, data->streams,
|
|
(data->k * sizeof(struct hdcp2_streamid_type)));
|
|
|
|
verify_mprime_in.k = cpu_to_be16(data->k);
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&verify_mprime_in,
|
|
sizeof(verify_mprime_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&verify_mprime_out,
|
|
sizeof(verify_mprime_out));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (verify_mprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
|
|
WIRED_REPEATER_AUTH_STREAM_REQ,
|
|
verify_mprime_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_enable_authentication() - Mark a port as authenticated
|
|
* through ME FW
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int mei_hdcp_enable_authentication(struct device *dev,
|
|
struct hdcp_port_data *data)
|
|
{
|
|
struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } };
|
|
struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !data)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
enable_auth_in.header.api_version = HDCP_API_VERSION;
|
|
enable_auth_in.header.command_id = WIRED_ENABLE_AUTH;
|
|
enable_auth_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
|
|
|
|
enable_auth_in.port.integrated_port_type = data->port_type;
|
|
enable_auth_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
enable_auth_in.stream_type = data->streams[0].stream_type;
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in,
|
|
sizeof(enable_auth_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&enable_auth_out,
|
|
sizeof(enable_auth_out));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (enable_auth_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
|
|
WIRED_ENABLE_AUTH, enable_auth_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mei_hdcp_close_session() - Close the Wired HDCP Tx session of ME FW per port.
|
|
* This also disables the authenticated state of the port.
|
|
* @dev: device corresponding to the mei_cl_device
|
|
* @data: Intel HW specific hdcp data
|
|
*
|
|
* Return: 0 on Success, <0 on Failure
|
|
*/
|
|
static int
|
|
mei_hdcp_close_session(struct device *dev, struct hdcp_port_data *data)
|
|
{
|
|
struct wired_cmd_close_session_in session_close_in = { { 0 } };
|
|
struct wired_cmd_close_session_out session_close_out = { { 0 } };
|
|
struct mei_cl_device *cldev;
|
|
ssize_t byte;
|
|
|
|
if (!dev || !data)
|
|
return -EINVAL;
|
|
|
|
cldev = to_mei_cl_device(dev);
|
|
|
|
session_close_in.header.api_version = HDCP_API_VERSION;
|
|
session_close_in.header.command_id = WIRED_CLOSE_SESSION;
|
|
session_close_in.header.status = ME_HDCP_STATUS_SUCCESS;
|
|
session_close_in.header.buffer_len =
|
|
WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
|
|
|
|
session_close_in.port.integrated_port_type = data->port_type;
|
|
session_close_in.port.physical_port = mei_get_ddi_index(data->port);
|
|
|
|
byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
|
|
sizeof(session_close_in));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
byte = mei_cldev_recv(cldev, (u8 *)&session_close_out,
|
|
sizeof(session_close_out));
|
|
if (byte < 0) {
|
|
dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
|
|
return byte;
|
|
}
|
|
|
|
if (session_close_out.header.status != ME_HDCP_STATUS_SUCCESS) {
|
|
dev_dbg(dev, "Session Close Failed. status: 0x%X\n",
|
|
session_close_out.header.status);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct i915_hdcp_component_ops mei_hdcp_ops = {
|
|
.owner = THIS_MODULE,
|
|
.initiate_hdcp2_session = mei_hdcp_initiate_session,
|
|
.verify_receiver_cert_prepare_km =
|
|
mei_hdcp_verify_receiver_cert_prepare_km,
|
|
.verify_hprime = mei_hdcp_verify_hprime,
|
|
.store_pairing_info = mei_hdcp_store_pairing_info,
|
|
.initiate_locality_check = mei_hdcp_initiate_locality_check,
|
|
.verify_lprime = mei_hdcp_verify_lprime,
|
|
.get_session_key = mei_hdcp_get_session_key,
|
|
.repeater_check_flow_prepare_ack =
|
|
mei_hdcp_repeater_check_flow_prepare_ack,
|
|
.verify_mprime = mei_hdcp_verify_mprime,
|
|
.enable_hdcp_authentication = mei_hdcp_enable_authentication,
|
|
.close_hdcp_session = mei_hdcp_close_session,
|
|
};
|
|
|
|
static int mei_component_master_bind(struct device *dev)
|
|
{
|
|
struct mei_cl_device *cldev = to_mei_cl_device(dev);
|
|
struct i915_hdcp_comp_master *comp_master =
|
|
mei_cldev_get_drvdata(cldev);
|
|
int ret;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
comp_master->ops = &mei_hdcp_ops;
|
|
comp_master->mei_dev = dev;
|
|
ret = component_bind_all(dev, comp_master);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mei_component_master_unbind(struct device *dev)
|
|
{
|
|
struct mei_cl_device *cldev = to_mei_cl_device(dev);
|
|
struct i915_hdcp_comp_master *comp_master =
|
|
mei_cldev_get_drvdata(cldev);
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
component_unbind_all(dev, comp_master);
|
|
}
|
|
|
|
static const struct component_master_ops mei_component_master_ops = {
|
|
.bind = mei_component_master_bind,
|
|
.unbind = mei_component_master_unbind,
|
|
};
|
|
|
|
static int mei_hdcp_component_match(struct device *dev, int subcomponent,
|
|
void *data)
|
|
{
|
|
return !strcmp(dev->driver->name, "i915") &&
|
|
subcomponent == I915_COMPONENT_HDCP;
|
|
}
|
|
|
|
static int mei_hdcp_probe(struct mei_cl_device *cldev,
|
|
const struct mei_cl_device_id *id)
|
|
{
|
|
struct i915_hdcp_comp_master *comp_master;
|
|
struct component_match *master_match;
|
|
int ret;
|
|
|
|
ret = mei_cldev_enable(cldev);
|
|
if (ret < 0) {
|
|
dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
|
|
goto enable_err_exit;
|
|
}
|
|
|
|
comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
|
|
if (!comp_master) {
|
|
ret = -ENOMEM;
|
|
goto err_exit;
|
|
}
|
|
|
|
master_match = NULL;
|
|
component_match_add_typed(&cldev->dev, &master_match,
|
|
mei_hdcp_component_match, comp_master);
|
|
if (IS_ERR_OR_NULL(master_match)) {
|
|
ret = -ENOMEM;
|
|
goto err_exit;
|
|
}
|
|
|
|
mei_cldev_set_drvdata(cldev, comp_master);
|
|
ret = component_master_add_with_match(&cldev->dev,
|
|
&mei_component_master_ops,
|
|
master_match);
|
|
if (ret < 0) {
|
|
dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
|
|
goto err_exit;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_exit:
|
|
mei_cldev_set_drvdata(cldev, NULL);
|
|
kfree(comp_master);
|
|
mei_cldev_disable(cldev);
|
|
enable_err_exit:
|
|
return ret;
|
|
}
|
|
|
|
static int mei_hdcp_remove(struct mei_cl_device *cldev)
|
|
{
|
|
struct i915_hdcp_comp_master *comp_master =
|
|
mei_cldev_get_drvdata(cldev);
|
|
|
|
component_master_del(&cldev->dev, &mei_component_master_ops);
|
|
kfree(comp_master);
|
|
mei_cldev_set_drvdata(cldev, NULL);
|
|
|
|
return mei_cldev_disable(cldev);
|
|
}
|
|
|
|
#define MEI_UUID_HDCP GUID_INIT(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \
|
|
0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
|
|
|
|
static struct mei_cl_device_id mei_hdcp_tbl[] = {
|
|
{ .uuid = MEI_UUID_HDCP, .version = MEI_CL_VERSION_ANY },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(mei, mei_hdcp_tbl);
|
|
|
|
static struct mei_cl_driver mei_hdcp_driver = {
|
|
.id_table = mei_hdcp_tbl,
|
|
.name = KBUILD_MODNAME,
|
|
.probe = mei_hdcp_probe,
|
|
.remove = mei_hdcp_remove,
|
|
};
|
|
|
|
module_mei_cl_driver(mei_hdcp_driver);
|
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("MEI HDCP");
|