mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 13:32:03 +07:00
b3a0317e31
Enable PCIe Controller & set PCIe bus clock frequency. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
187 lines
3.0 KiB
Plaintext
187 lines
3.0 KiB
Plaintext
/*
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* Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
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*
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* Copyright (C) 2017 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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aliases {
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serial0 = &scif0;
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serial3 = &scifb1;
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ethernet0 = &avb;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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vcc_sdhi1: regulator-vcc-sdhi1 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI1 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
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};
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vccq_sdhi1: regulator-vccq-sdhi1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI1 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy3>;
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phy-mode = "gmii";
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renesas,no-ether-link;
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status = "okay";
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phy3: ethernet-phy@3 {
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reg = <3>;
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micrel,led-mode = <1>;
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};
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&hsusb {
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status = "okay";
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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rtc@68 {
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compatible = "ti,bq32000";
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reg = <0x68>;
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};
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};
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&pci0 {
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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};
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&pci1 {
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status = "okay";
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pinctrl-0 = <&usb1_pins>;
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pinctrl-names = "default";
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pciec {
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status = "okay";
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};
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&pfc {
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can0_pins: can0 {
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groups = "can0_data_d";
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function = "can0";
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};
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avb_pins: avb {
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groups = "avb_mdio", "avb_gmii";
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function = "avb";
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};
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i2c2_pins: i2c2 {
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groups = "i2c2";
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function = "i2c2";
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};
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scif0_pins: scif0 {
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groups = "scif0_data_d";
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function = "scif0";
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};
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scifb1_pins: scifb1 {
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groups = "scifb1_data_d", "scifb1_ctrl";
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function = "scifb1";
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};
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sdhi1_pins: sd1 {
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groups = "sdhi1_data4", "sdhi1_ctrl";
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function = "sdhi1";
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power-source = <3300>;
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};
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sdhi1_pins_uhs: sd1_uhs {
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groups = "sdhi1_data4", "sdhi1_ctrl";
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function = "sdhi1";
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power-source = <1800>;
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};
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usb0_pins: usb0 {
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groups = "usb0";
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function = "usb0";
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};
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usb1_pins: usb1 {
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groups = "usb1";
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function = "usb1";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scifb1 {
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pinctrl-0 = <&scifb1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&sdhi1 {
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pinctrl-0 = <&sdhi1_pins>;
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pinctrl-1 = <&sdhi1_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi1>;
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vqmmc-supply = <&vccq_sdhi1>;
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cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
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sd-uhs-sdr50;
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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