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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9b17e5ad78
The dev *ss is stored both in sun4i_tfm_ctx and sun4i_req_ctx. Since this pointer will never be changed during tfm life, it is better to remove it from sun4i_req_ctx. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
202 lines
5.5 KiB
C
202 lines
5.5 KiB
C
/*
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* sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
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*
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* Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
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*
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* Support AES cipher with 128,192,256 bits keysize.
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* Support MD5 and SHA1 hash algorithms.
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* Support DES and 3DES
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*
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* You could find the datasheet in Documentation/arm/sunxi/README
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/clk.h>
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#include <linux/crypto.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <crypto/scatterwalk.h>
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#include <linux/scatterlist.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <crypto/md5.h>
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#include <crypto/sha.h>
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#include <crypto/hash.h>
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#include <crypto/internal/hash.h>
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#include <crypto/aes.h>
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#include <crypto/des.h>
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#include <crypto/internal/rng.h>
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#define SS_CTL 0x00
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#define SS_KEY0 0x04
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#define SS_KEY1 0x08
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#define SS_KEY2 0x0C
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#define SS_KEY3 0x10
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#define SS_KEY4 0x14
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#define SS_KEY5 0x18
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#define SS_KEY6 0x1C
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#define SS_KEY7 0x20
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#define SS_IV0 0x24
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#define SS_IV1 0x28
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#define SS_IV2 0x2C
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#define SS_IV3 0x30
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#define SS_FCSR 0x44
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#define SS_MD0 0x4C
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#define SS_MD1 0x50
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#define SS_MD2 0x54
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#define SS_MD3 0x58
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#define SS_MD4 0x5C
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#define SS_RXFIFO 0x200
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#define SS_TXFIFO 0x204
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/* SS_CTL configuration values */
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/* PRNG generator mode - bit 15 */
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#define SS_PRNG_ONESHOT (0 << 15)
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#define SS_PRNG_CONTINUE (1 << 15)
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/* IV mode for hash */
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#define SS_IV_ARBITRARY (1 << 14)
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/* SS operation mode - bits 12-13 */
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#define SS_ECB (0 << 12)
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#define SS_CBC (1 << 12)
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#define SS_CTS (3 << 12)
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/* Counter width for CNT mode - bits 10-11 */
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#define SS_CNT_16BITS (0 << 10)
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#define SS_CNT_32BITS (1 << 10)
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#define SS_CNT_64BITS (2 << 10)
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/* Key size for AES - bits 8-9 */
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#define SS_AES_128BITS (0 << 8)
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#define SS_AES_192BITS (1 << 8)
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#define SS_AES_256BITS (2 << 8)
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/* Operation direction - bit 7 */
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#define SS_ENCRYPTION (0 << 7)
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#define SS_DECRYPTION (1 << 7)
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/* SS Method - bits 4-6 */
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#define SS_OP_AES (0 << 4)
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#define SS_OP_DES (1 << 4)
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#define SS_OP_3DES (2 << 4)
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#define SS_OP_SHA1 (3 << 4)
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#define SS_OP_MD5 (4 << 4)
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#define SS_OP_PRNG (5 << 4)
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/* Data end bit - bit 2 */
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#define SS_DATA_END (1 << 2)
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/* PRNG start bit - bit 1 */
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#define SS_PRNG_START (1 << 1)
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/* SS Enable bit - bit 0 */
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#define SS_DISABLED (0 << 0)
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#define SS_ENABLED (1 << 0)
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/* SS_FCSR configuration values */
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/* RX FIFO status - bit 30 */
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#define SS_RXFIFO_FREE (1 << 30)
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/* RX FIFO empty spaces - bits 24-29 */
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#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
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/* TX FIFO status - bit 22 */
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#define SS_TXFIFO_AVAILABLE (1 << 22)
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/* TX FIFO available spaces - bits 16-21 */
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#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
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#define SS_RX_MAX 32
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#define SS_RX_DEFAULT SS_RX_MAX
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#define SS_TX_MAX 33
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#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
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#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
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#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
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#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
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struct sun4i_ss_ctx {
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void __iomem *base;
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int irq;
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struct clk *busclk;
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struct clk *ssclk;
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struct reset_control *reset;
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struct device *dev;
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struct resource *res;
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spinlock_t slock; /* control the use of the device */
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};
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struct sun4i_ss_alg_template {
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u32 type;
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u32 mode;
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union {
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struct crypto_alg crypto;
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struct ahash_alg hash;
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} alg;
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struct sun4i_ss_ctx *ss;
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};
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struct sun4i_tfm_ctx {
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u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
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u32 keylen;
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u32 keymode;
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struct sun4i_ss_ctx *ss;
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};
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struct sun4i_cipher_req_ctx {
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u32 mode;
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};
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struct sun4i_req_ctx {
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u32 mode;
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u64 byte_count; /* number of bytes "uploaded" to the device */
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u32 hash[5]; /* for storing SS_IVx register */
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char buf[64];
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unsigned int len;
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int flags;
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};
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int sun4i_hash_crainit(struct crypto_tfm *tfm);
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int sun4i_hash_init(struct ahash_request *areq);
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int sun4i_hash_update(struct ahash_request *areq);
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int sun4i_hash_final(struct ahash_request *areq);
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int sun4i_hash_finup(struct ahash_request *areq);
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int sun4i_hash_digest(struct ahash_request *areq);
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int sun4i_hash_export_md5(struct ahash_request *areq, void *out);
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int sun4i_hash_import_md5(struct ahash_request *areq, const void *in);
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int sun4i_hash_export_sha1(struct ahash_request *areq, void *out);
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int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in);
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int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq);
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int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq);
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int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
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int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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unsigned int keylen);
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int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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unsigned int keylen);
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int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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unsigned int keylen);
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