mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 23:36:39 +07:00
2c856e14da
- Initial support for ARMv8.1 CPU PMUs - Support for the CPU PMU in Cavium ThunderX - CPU PMU support for systems running 32-bit Linux in secure mode - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJW794rAAoJELescNyEwWM0O5IH/0ejoUjip3n4dFZnSzAbQQZe VxCy3DXW5gS8YaswwX2dFw9K772/BpHlazq8AIJIhaR+b+Zzl5t0iOc12HluDilV pMvi0JTCxwJhsEiKZnP0cVAU9HM6MAgtMOEegkd/YNESKQey30NeDtIcz/pQfTUV 28AF71+w5VPj/1EpHEEhHQsASRIx7eDbKzThzdlb8PnDS0o23QJhL9HjVTNIAlB8 BGxrUBKtBu0eH2Hx33vNjc7UYx1WZQlCk5cAaXevA8mbFXzYaMQI2Cel2nbNMO9i eu5zPkDUCG7dq16PxK6IgM4AsDCtmmDuckLdN6UEQWYxkLbb2qHNRKtj0bKB8Sk= =E4PE -----END PGP SIGNATURE----- Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm[64] perf updates from Will Deacon: "I have another mixed bag of ARM-related perf patches here. It's about 25% CPU and 75% interconnect, but with drivers/bus/ languishing without an obvious maintainer or tree, Olof and I agreed to keep all of these PMU patches together. I suspect a whole load of code from drivers/bus/arm-* can be moved under drivers/perf/, so that's on the radar for the future. Summary: - Initial support for ARMv8.1 CPU PMUs - Support for the CPU PMU in Cavium ThunderX - CPU PMU support for systems running 32-bit Linux in secure mode - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)" * tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits) drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC arm-cci: remove unused variable arm-cci: don't return value from void function arm-cci: make private functions static arm-cci: CoreLink CCI-550 PMU driver arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU arm-cci: CCI-500: Work around PMU counter writes arm-cci: Provide hook for writing to PMU counters arm-cci: Add helper to enable PMU without synchornising counters arm-cci: Add routines to save/restore all counters arm-cci: Get the status of a counter arm-cci: write_counter: Remove redundant check arm-cci: Delay PMU counter writes to pmu::pmu_enable arm-cci: Refactor CCI PMU enable/disable methods arm-cci: Group writes to counter arm-cci: fix handling cpumask_any_but return value arm-cci: simplify sysfs attr handling drivers/perf: arm_pmu: implement CPU_PM notifier arm64: dts: Add Cavium ThunderX specific PMU ...
152 lines
4.3 KiB
Plaintext
152 lines
4.3 KiB
Plaintext
#
|
|
# Bus Devices
|
|
#
|
|
|
|
menu "Bus devices"
|
|
|
|
config ARM_CCI
|
|
bool
|
|
|
|
config ARM_CCI_PMU
|
|
bool
|
|
select ARM_CCI
|
|
|
|
config ARM_CCI400_COMMON
|
|
bool
|
|
select ARM_CCI
|
|
|
|
config ARM_CCI400_PMU
|
|
bool "ARM CCI400 PMU support"
|
|
depends on (ARM && CPU_V7) || ARM64
|
|
depends on PERF_EVENTS
|
|
select ARM_CCI400_COMMON
|
|
select ARM_CCI_PMU
|
|
help
|
|
Support for PMU events monitoring on the ARM CCI-400 (cache coherent
|
|
interconnect). CCI-400 supports counting events related to the
|
|
connected slave/master interfaces.
|
|
|
|
config ARM_CCI400_PORT_CTRL
|
|
bool
|
|
depends on ARM && OF && CPU_V7
|
|
select ARM_CCI400_COMMON
|
|
help
|
|
Low level power management driver for CCI400 cache coherent
|
|
interconnect for ARM platforms.
|
|
|
|
config ARM_CCI5xx_PMU
|
|
bool "ARM CCI-500/CCI-550 PMU support"
|
|
depends on (ARM && CPU_V7) || ARM64
|
|
depends on PERF_EVENTS
|
|
select ARM_CCI_PMU
|
|
help
|
|
Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache
|
|
coherent interconnects. Both of them provide 8 independent event counters,
|
|
which can count events pertaining to the slave/master interfaces as well
|
|
as the internal events to the CCI.
|
|
|
|
If unsure, say Y
|
|
|
|
config ARM_CCN
|
|
bool "ARM CCN driver support"
|
|
depends on ARM || ARM64
|
|
depends on PERF_EVENTS
|
|
help
|
|
PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
|
|
interconnect.
|
|
|
|
config BRCMSTB_GISB_ARB
|
|
bool "Broadcom STB GISB bus arbiter"
|
|
depends on ARM || MIPS
|
|
help
|
|
Driver for the Broadcom Set Top Box System-on-a-chip internal bus
|
|
arbiter. This driver provides timeout and target abort error handling
|
|
and internal bus master decoding.
|
|
|
|
config IMX_WEIM
|
|
bool "Freescale EIM DRIVER"
|
|
depends on ARCH_MXC
|
|
help
|
|
Driver for i.MX WEIM controller.
|
|
The WEIM(Wireless External Interface Module) works like a bus.
|
|
You can attach many different devices on it, such as NOR, onenand.
|
|
|
|
config MIPS_CDMM
|
|
bool "MIPS Common Device Memory Map (CDMM) Driver"
|
|
depends on CPU_MIPSR2
|
|
help
|
|
Driver needed for the MIPS Common Device Memory Map bus in MIPS
|
|
cores. This bus is for per-CPU tightly coupled devices such as the
|
|
Fast Debug Channel (FDC).
|
|
|
|
For this to work, either your bootloader needs to enable the CDMM
|
|
region at an unused physical address on the boot CPU, or else your
|
|
platform code needs to implement mips_cdmm_phys_base() (see
|
|
asm/cdmm.h).
|
|
|
|
config MVEBU_MBUS
|
|
bool
|
|
depends on PLAT_ORION
|
|
help
|
|
Driver needed for the MBus configuration on Marvell EBU SoCs
|
|
(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
|
|
|
|
config OMAP_INTERCONNECT
|
|
tristate "OMAP INTERCONNECT DRIVER"
|
|
depends on ARCH_OMAP2PLUS
|
|
|
|
help
|
|
Driver to enable OMAP interconnect error handling driver.
|
|
|
|
config OMAP_OCP2SCP
|
|
tristate "OMAP OCP2SCP DRIVER"
|
|
depends on ARCH_OMAP2PLUS
|
|
help
|
|
Driver to enable ocp2scp module which transforms ocp interface
|
|
protocol to scp protocol. In OMAP4, USB PHY is connected via
|
|
OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
|
|
OCP2SCP.
|
|
|
|
config SIMPLE_PM_BUS
|
|
bool "Simple Power-Managed Bus Driver"
|
|
depends on OF && PM
|
|
depends on ARCH_SHMOBILE || COMPILE_TEST
|
|
help
|
|
Driver for transparent busses that don't need a real driver, but
|
|
where the bus controller is part of a PM domain, or under the control
|
|
of a functional clock, and thus relies on runtime PM for managing
|
|
this PM domain and/or clock.
|
|
An example of such a bus controller is the Renesas Bus State
|
|
Controller (BSC, sometimes called "LBSC within Bus Bridge", or
|
|
"External Bus Interface") as found on several Renesas ARM SoCs.
|
|
|
|
config SUNXI_RSB
|
|
tristate "Allwinner sunXi Reduced Serial Bus Driver"
|
|
default MACH_SUN8I || MACH_SUN9I
|
|
depends on ARCH_SUNXI
|
|
select REGMAP
|
|
help
|
|
Say y here to enable support for Allwinner's Reduced Serial Bus
|
|
(RSB) support. This controller is responsible for communicating
|
|
with various RSB based devices, such as AXP223, AXP8XX PMICs,
|
|
and AC100/AC200 ICs.
|
|
|
|
config UNIPHIER_SYSTEM_BUS
|
|
tristate "UniPhier System Bus driver"
|
|
depends on ARCH_UNIPHIER && OF
|
|
default y
|
|
help
|
|
Support for UniPhier System Bus, a simple external bus. This is
|
|
needed to use on-board devices connected to UniPhier SoCs.
|
|
|
|
config VEXPRESS_CONFIG
|
|
bool "Versatile Express configuration bus"
|
|
default y if ARCH_VEXPRESS
|
|
depends on ARM || ARM64
|
|
depends on OF
|
|
select REGMAP
|
|
help
|
|
Platform configuration infrastructure for the ARM Ltd.
|
|
Versatile Express.
|
|
endmenu
|