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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c7c0e7ebe4
Encapsulate the dbuf state more by moving the pre/post plane functions out from intel_display.c. We stick them into intel_pm.c since that's where the rest of the code lives for now. Eventually we should add a new file for this stuff at which point we also need to decide if it makes sense to even split the wm code from the ddb code, or to keep them together. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200225171125.28885-11-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
90 lines
3.4 KiB
C
90 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PM_H__
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#define __INTEL_PM_H__
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#include <linux/types.h>
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#include "display/intel_global_state.h"
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#include "i915_reg.h"
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#include "display/intel_bw.h"
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struct drm_device;
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struct drm_i915_private;
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struct i915_request;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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void intel_init_clock_gating(struct drm_i915_private *dev_priv);
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void intel_suspend_hw(struct drm_i915_private *dev_priv);
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int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
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void intel_update_watermarks(struct intel_crtc *crtc);
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void intel_init_pm(struct drm_i915_private *dev_priv);
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
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void intel_pm_setup(struct drm_i915_private *dev_priv);
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void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb_uv);
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void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
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struct skl_pipe_wm *out);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state);
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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const struct skl_wm_level *l2);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
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void intel_init_ipc(struct drm_i915_private *dev_priv);
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void intel_enable_ipc(struct drm_i915_private *dev_priv);
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bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
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struct intel_dbuf_state {
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struct intel_global_state base;
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u8 enabled_slices;
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u8 active_pipes;
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};
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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#endif /* __INTEL_PM_H__ */
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