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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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24ce2705c2
For still better multi-OMAP1 support, expand omap1_rate_table with flags for different SoC types and match them while selecting clock rates. The idea is stolen from current omap24xx clock rate selection algorithm. Since clkdev platform flag definitions are reused here, those had to be expanded with one extra entry for OMAP1710 subtype, as this is the only SoC for which we allow selection of the highest, 216 MHz rate. Once done, remove no longer needed clock rate configure time options. Tested on Amstrad Delta. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> [tony@atomide.com: updated comments] Signed-off-by: Tony Lindgren <tony@atomide.com>
118 lines
3.9 KiB
C
118 lines
3.9 KiB
C
/*
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* linux/arch/arm/mach-omap1/clock.h
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*
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* Copyright (C) 2004 - 2005, 2009 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#include <linux/clk.h>
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#include <plat/clock.h>
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int omap1_clk_init(void);
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void omap1_clk_late_init(void);
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extern int omap1_clk_enable(struct clk *clk);
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extern void omap1_clk_disable(struct clk *clk);
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extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
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extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_ckctl_recalc(struct clk *clk);
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extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_sossi_recalc(struct clk *clk);
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extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
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extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
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extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_uart_recalc(struct clk *clk);
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extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
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extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
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extern void omap1_init_ext_clk(struct clk *clk);
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extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
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extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
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extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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extern unsigned long omap1_watchdog_recalc(struct clk *clk);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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extern void omap1_clk_disable_unused(struct clk *clk);
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#else
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#define omap1_clk_disable_unused NULL
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#endif
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struct uart_clk {
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struct clk clk;
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unsigned long sysc_addr;
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};
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/* Provide a method for preventing idling some ARM IDLECT clocks */
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struct arm_idlect1_clk {
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struct clk clk;
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unsigned long no_idle_count;
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__u8 idlect_shift;
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};
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/* ARM_CKCTL bit shifts */
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#define CKCTL_PERDIV_OFFSET 0
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#define CKCTL_LCDDIV_OFFSET 2
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#define CKCTL_ARMDIV_OFFSET 4
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#define CKCTL_DSPDIV_OFFSET 6
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#define CKCTL_TCDIV_OFFSET 8
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#define CKCTL_DSPMMUDIV_OFFSET 10
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/*#define ARM_TIMXO 12*/
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#define EN_DSPCK 13
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/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
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/* DSP_CKCTL bit shifts */
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#define CKCTL_DSPPERDIV_OFFSET 0
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/* ARM_IDLECT2 bit shifts */
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#define EN_WDTCK 0
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#define EN_XORPCK 1
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#define EN_PERCK 2
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#define EN_LCDCK 3
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#define EN_LBCK 4 /* Not on 1610/1710 */
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/*#define EN_HSABCK 5*/
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#define EN_APICK 6
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#define EN_TIMCK 7
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#define DMACK_REQ 8
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#define EN_GPIOCK 9 /* Not on 1610/1710 */
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/*#define EN_LBFREECK 10*/
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#define EN_CKOUT_ARM 11
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/* ARM_IDLECT3 bit shifts */
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#define EN_OCPI_CK 0
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#define EN_TC1_CK 2
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#define EN_TC2_CK 4
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/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
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#define EN_DSPTIMCK 5
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/* Various register defines for clock controls scattered around OMAP chip */
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#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
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#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
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#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
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#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
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#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
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#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
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#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
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#define SOFT_REQ_REG 0xfffe0834
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#define SOFT_REQ_REG2 0xfffe0880
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extern __u32 arm_idlect1_mask;
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extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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extern const struct clkops clkops_dspck;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_uart_16xx;
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extern const struct clkops clkops_generic;
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/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
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extern u32 cpu_mask;
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#endif
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