mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 21:25:33 +07:00
27aa64b9d1
Add missing clk_put() call to ata_host_activate() failure path.
Sergei says,
"Hm, I have once fixed that (see that *if* (!ret)) but looks like a
later commit 477c87e908
(ARM:
at91/pata: use gpio_is_valid to check the gpio) broke it again. :-(
Would be good if the changelog did mention that..."
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: stable@vger.kernel.org
458 lines
12 KiB
C
458 lines
12 KiB
C
/*
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* PATA driver for AT91SAM9260 Static Memory Controller
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* with CompactFlash interface in True IDE mode
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*
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* Copyright (C) 2009 Matyukevich Sergey
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* 2011 Igor Plyatov
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*
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* Based on:
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* * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
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* * pata_at32 driver by Kristoffer Nyborg Gregertsen
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* * at91_ide driver by Stanislaw Gruszka
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/blkdev.h>
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#include <linux/gfp.h>
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#include <scsi/scsi_host.h>
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#include <linux/ata.h>
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#include <linux/clk.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/platform_data/atmel.h>
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#include <mach/at91sam9_smc.h>
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#include <asm/gpio.h>
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#define DRV_NAME "pata_at91"
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#define DRV_VERSION "0.3"
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#define CF_IDE_OFFSET 0x00c00000
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#define CF_ALT_IDE_OFFSET 0x00e00000
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#define CF_IDE_RES_SIZE 0x08
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#define CS_PULSE_MAXIMUM 319
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#define ER_SMC_CALC 1
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#define ER_SMC_RECALC 2
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struct at91_ide_info {
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unsigned long mode;
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unsigned int cs;
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struct clk *mck;
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void __iomem *ide_addr;
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void __iomem *alt_addr;
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};
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/**
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* struct smc_range - range of valid values for SMC register.
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*/
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struct smc_range {
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int min;
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int max;
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};
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/**
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* adjust_smc_value - adjust value for one of SMC registers.
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* @value: adjusted value
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* @range: array of SMC ranges with valid values
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* @size: SMC ranges array size
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*
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* This returns the difference between input and output value or negative
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* in case of invalid input value.
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* If negative returned, then output value = maximal possible from ranges.
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*/
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static int adjust_smc_value(int *value, struct smc_range *range, int size)
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{
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int maximum = (range + size - 1)->max;
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int remainder;
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do {
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if (*value < range->min) {
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remainder = range->min - *value;
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*value = range->min; /* nearest valid value */
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return remainder;
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} else if ((range->min <= *value) && (*value <= range->max))
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return 0;
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range++;
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} while (--size);
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*value = maximum;
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return -1; /* invalid value */
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}
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/**
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* calc_smc_vals - calculate SMC register values
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* @dev: ATA device
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* @setup: SMC_SETUP register value
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* @pulse: SMC_PULSE register value
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* @cycle: SMC_CYCLE register value
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*
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* This returns negative in case of invalid values for SMC registers:
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* -ER_SMC_RECALC - recalculation required for SMC values,
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* -ER_SMC_CALC - calculation failed (invalid input values).
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*
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* SMC use special coding scheme, see "Coding and Range of Timing
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* Parameters" table from AT91SAM9 datasheets.
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*
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* SMC_SETUP = 128*setup[5] + setup[4:0]
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* SMC_PULSE = 256*pulse[6] + pulse[5:0]
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* SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
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*/
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static int calc_smc_vals(struct device *dev,
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int *setup, int *pulse, int *cycle, int *cs_pulse)
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{
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int ret_val;
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int err = 0;
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struct smc_range range_setup[] = { /* SMC_SETUP valid values */
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{.min = 0, .max = 31}, /* first range */
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{.min = 128, .max = 159} /* second range */
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};
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struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
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{.min = 0, .max = 63}, /* first range */
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{.min = 256, .max = 319} /* second range */
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};
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struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
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{.min = 0, .max = 127}, /* first range */
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{.min = 256, .max = 383}, /* second range */
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{.min = 512, .max = 639}, /* third range */
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{.min = 768, .max = 895} /* fourth range */
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};
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ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Setup value\n");
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else
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*cycle += ret_val;
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ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Pulse value\n");
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else
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*cycle += ret_val;
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ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Cycle value\n");
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*cs_pulse = *cycle;
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if (*cs_pulse > CS_PULSE_MAXIMUM) {
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dev_err(dev, "unable to calculate valid SMC settings\n");
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return -ER_SMC_CALC;
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}
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ret_val = adjust_smc_value(cs_pulse, range_pulse,
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ARRAY_SIZE(range_pulse));
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if (ret_val < 0) {
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dev_warn(dev, "maximal SMC CS Pulse value\n");
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} else if (ret_val != 0) {
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*cycle = *cs_pulse;
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dev_warn(dev, "SMC Cycle extended\n");
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err = -ER_SMC_RECALC;
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}
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return err;
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}
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/**
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* to_smc_format - convert values into SMC format
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* @setup: SETUP value of SMC Setup Register
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* @pulse: PULSE value of SMC Pulse Register
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* @cycle: CYCLE value of SMC Cycle Register
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* @cs_pulse: NCS_PULSE value of SMC Pulse Register
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*/
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static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
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{
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*setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
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*pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
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*cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
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*cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
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}
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static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
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{
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unsigned long mul;
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/*
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* cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
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* x * (f / 1_000_000_000) =
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* x * ((f * 65536) / 1_000_000_000) / 65536 =
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* x * (((f / 10_000) * 65536) / 100_000) / 65536 =
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*/
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mul = (mck_hz / 10000) << 16;
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mul /= 100000;
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return (ns * mul + 65536) >> 16; /* rounding */
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}
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/**
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* set_smc_timing - SMC timings setup.
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* @dev: device
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* @info: AT91 IDE info
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* @ata: ATA timings
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*
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* Its assumed that write timings are same as read timings,
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* cs_setup = 0 and cs_pulse = cycle.
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*/
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static void set_smc_timing(struct device *dev, struct ata_device *adev,
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struct at91_ide_info *info, const struct ata_timing *ata)
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{
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int ret = 0;
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int use_iordy;
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struct sam9_smc_config smc;
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unsigned int t6z; /* data tristate time in ns */
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unsigned int cycle; /* SMC Cycle width in MCK ticks */
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unsigned int setup; /* SMC Setup width in MCK ticks */
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unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
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unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
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unsigned int tdf_cycles; /* SMC TDF MCK ticks */
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unsigned long mck_hz; /* MCK frequency in Hz */
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t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
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mck_hz = clk_get_rate(info->mck);
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cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
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setup = calc_mck_cycles(ata->setup, mck_hz);
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pulse = calc_mck_cycles(ata->act8b, mck_hz);
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tdf_cycles = calc_mck_cycles(t6z, mck_hz);
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do {
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ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
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} while (ret == -ER_SMC_RECALC);
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if (ret == -ER_SMC_CALC)
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dev_err(dev, "Interface may not operate correctly\n");
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dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
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setup, pulse, cycle, cs_pulse);
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to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
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/* disable or enable waiting for IORDY signal */
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use_iordy = ata_pio_need_iordy(adev);
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if (use_iordy)
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info->mode |= AT91_SMC_EXNWMODE_READY;
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if (tdf_cycles > 15) {
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tdf_cycles = 15;
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dev_warn(dev, "maximal SMC TDF Cycles value\n");
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}
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dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
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/* SMC Setup Register */
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smc.nwe_setup = smc.nrd_setup = setup;
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smc.ncs_write_setup = smc.ncs_read_setup = 0;
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/* SMC Pulse Register */
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smc.nwe_pulse = smc.nrd_pulse = pulse;
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smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
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/* SMC Cycle Register */
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smc.write_cycle = smc.read_cycle = cycle;
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/* SMC Mode Register*/
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smc.tdf_cycles = tdf_cycles;
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smc.mode = info->mode;
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sam9_smc_configure(0, info->cs, &smc);
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}
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static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct at91_ide_info *info = ap->host->private_data;
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struct ata_timing timing;
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int ret;
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/* Compute ATA timing and set it to SMC */
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ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
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if (ret) {
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dev_warn(ap->dev, "Failed to compute ATA timing %d, "
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"set PIO_0 timing\n", ret);
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timing = *ata_timing_find_mode(XFER_PIO_0);
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}
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set_smc_timing(ap->dev, adev, info, &timing);
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}
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static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
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unsigned char *buf, unsigned int buflen, int rw)
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{
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struct at91_ide_info *info = dev->link->ap->host->private_data;
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unsigned int consumed;
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unsigned long flags;
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struct sam9_smc_config smc;
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local_irq_save(flags);
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sam9_smc_read_mode(0, info->cs, &smc);
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/* set 16bit mode before writing data */
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smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16;
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sam9_smc_write_mode(0, info->cs, &smc);
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consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
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/* restore 8bit mode after data is written */
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smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8;
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sam9_smc_write_mode(0, info->cs, &smc);
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local_irq_restore(flags);
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return consumed;
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}
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static struct scsi_host_template pata_at91_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations pata_at91_port_ops = {
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.inherits = &ata_sff_port_ops,
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.sff_data_xfer = pata_at91_data_xfer_noirq,
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.set_piomode = pata_at91_set_piomode,
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.cable_detect = ata_cable_40wire,
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};
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static int pata_at91_probe(struct platform_device *pdev)
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{
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struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
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struct device *dev = &pdev->dev;
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struct at91_ide_info *info;
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struct resource *mem_res;
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struct ata_host *host;
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struct ata_port *ap;
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int irq_flags = 0;
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int irq = 0;
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int ret;
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/* get platform resources: IO/CTL memories and irq/rst pins */
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if (pdev->num_resources != 1) {
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dev_err(&pdev->dev, "invalid number of resources\n");
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return -EINVAL;
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}
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mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem_res) {
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dev_err(dev, "failed to get mem resource\n");
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return -EINVAL;
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}
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irq = board->irq_pin;
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/* init ata host */
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host = ata_host_alloc(dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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ap->ops = &pata_at91_port_ops;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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ap->pio_mask = ATA_PIO4;
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if (!gpio_is_valid(irq)) {
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ap->flags |= ATA_FLAG_PIO_POLLING;
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ata_port_desc(ap, "no IRQ, using PIO polling");
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}
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info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
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if (!info) {
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dev_err(dev, "failed to allocate memory for private data\n");
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return -ENOMEM;
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}
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info->mck = clk_get(NULL, "mck");
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if (IS_ERR(info->mck)) {
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dev_err(dev, "failed to get access to mck clock\n");
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return -ENODEV;
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}
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info->cs = board->chipselect;
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info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
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AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);
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info->ide_addr = devm_ioremap(dev,
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mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
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if (!info->ide_addr) {
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dev_err(dev, "failed to map IO base\n");
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ret = -ENOMEM;
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goto err_put;
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}
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info->alt_addr = devm_ioremap(dev,
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mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
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if (!info->alt_addr) {
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dev_err(dev, "failed to map CTL base\n");
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ret = -ENOMEM;
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goto err_put;
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}
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ap->ioaddr.cmd_addr = info->ide_addr;
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ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
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ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
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ata_sff_std_ports(&ap->ioaddr);
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ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
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(unsigned long long)mem_res->start + CF_IDE_OFFSET,
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(unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
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host->private_data = info;
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ret = ata_host_activate(host, gpio_is_valid(irq) ? gpio_to_irq(irq) : 0,
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gpio_is_valid(irq) ? ata_sff_interrupt : NULL,
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irq_flags, &pata_at91_sht);
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if (ret)
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goto err_put;
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return 0;
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err_put:
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clk_put(info->mck);
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return ret;
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}
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static int pata_at91_remove(struct platform_device *pdev)
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{
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struct ata_host *host = platform_get_drvdata(pdev);
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struct at91_ide_info *info;
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if (!host)
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return 0;
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info = host->private_data;
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ata_host_detach(host);
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if (!info)
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return 0;
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clk_put(info->mck);
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return 0;
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}
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static struct platform_driver pata_at91_driver = {
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.probe = pata_at91_probe,
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.remove = pata_at91_remove,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(pata_at91_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
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MODULE_AUTHOR("Matyukevich Sergey");
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MODULE_VERSION(DRV_VERSION);
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