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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4235ff50cf
Add device driver for a virtual programmable interrupt controller The virtual PIC is designed as a device tree-based interrupt controller. The compatible string used by OS for binding the driver is "google,goldfish-pic". Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by: Goran Ferenc <goran.ferenc@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* Driver for MIPS Goldfish Programmable Interrupt Controller.
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*
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* Author: Miodrag Dinic <miodrag.dinic@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define GFPIC_NR_IRQS 32
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/* 8..39 Cascaded Goldfish PIC interrupts */
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#define GFPIC_IRQ_BASE 8
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#define GFPIC_REG_IRQ_PENDING 0x04
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#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
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#define GFPIC_REG_IRQ_DISABLE 0x0c
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#define GFPIC_REG_IRQ_ENABLE 0x10
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struct goldfish_pic_data {
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void __iomem *base;
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struct irq_domain *irq_domain;
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};
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static void goldfish_pic_cascade(struct irq_desc *desc)
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{
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struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
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struct irq_chip *host_chip = irq_desc_get_chip(desc);
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u32 pending, hwirq, virq;
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chained_irq_enter(host_chip, desc);
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pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
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while (pending) {
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hwirq = __fls(pending);
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virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
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generic_handle_irq(virq);
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pending &= ~(1 << hwirq);
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}
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chained_irq_exit(host_chip, desc);
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}
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static const struct irq_domain_ops goldfish_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init goldfish_pic_of_init(struct device_node *of_node,
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struct device_node *parent)
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{
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struct goldfish_pic_data *gfpic;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int parent_irq;
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int ret = 0;
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gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
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if (!gfpic) {
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ret = -ENOMEM;
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goto out_err;
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}
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parent_irq = irq_of_parse_and_map(of_node, 0);
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if (!parent_irq) {
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pr_err("Failed to map parent IRQ!\n");
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ret = -EINVAL;
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goto out_free;
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}
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gfpic->base = of_iomap(of_node, 0);
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if (!gfpic->base) {
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pr_err("Failed to map base address!\n");
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ret = -ENOMEM;
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goto out_unmap_irq;
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}
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/* Mask interrupts. */
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writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
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gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
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handle_level_irq);
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if (!gc) {
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pr_err("Failed to allocate chip structures!\n");
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ret = -ENOMEM;
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goto out_iounmap;
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}
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ct = gc->chip_types;
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ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
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ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
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GFPIC_IRQ_BASE, 0,
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&goldfish_irq_domain_ops,
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NULL);
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if (!gfpic->irq_domain) {
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pr_err("Failed to add irqdomain!\n");
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ret = -ENOMEM;
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goto out_destroy_generic_chip;
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}
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irq_set_chained_handler_and_data(parent_irq,
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goldfish_pic_cascade, gfpic);
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pr_info("Successfully registered.\n");
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return 0;
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out_destroy_generic_chip:
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irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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out_iounmap:
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iounmap(gfpic->base);
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out_unmap_irq:
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irq_dispose_mapping(parent_irq);
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out_free:
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kfree(gfpic);
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out_err:
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pr_err("Failed to initialize! (errno = %d)\n", ret);
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return ret;
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}
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IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
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