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6dd9344cfc
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work. The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.
Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed. There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.
Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically. In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).
The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
229 lines
8.6 KiB
C
229 lines
8.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2002 by Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2002 Maciej W. Rozycki
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*/
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#ifndef _ASM_PGTABLE_BITS_H
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#define _ASM_PGTABLE_BITS_H
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/*
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* Note that we shift the lower 32bits of each EntryLo[01] entry
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* 6 bits to the left. That way we can convert the PFN into the
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* physical address by a single 'and' operation and gain 6 additional
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* bits for storing information which isn't present in a normal
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* MIPS page table.
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*
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* Similar to the Alpha port, we need to keep track of the ref
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* and mod bits in software. We have a software "yeah you can read
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* from this page" bit, and a hardware one which actually lets the
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* process read from the page. On the same token we have a software
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* writable bit and the real hardware one which actually lets the
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* process write to the page, this keeps a mod bit via the hardware
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* dirty bit.
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*
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* Certain revisions of the R4000 and R5000 have a bug where if a
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* certain sequence occurs in the last 3 instructions of an executable
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* page, and the following page is not mapped, the cpu can do
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* unpredictable things. The code (when it is written) to deal with
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* this problem will be in the update_mmu_cache() code for the r4k.
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*/
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define _PAGE_PRESENT (1<<6) /* implemented in software */
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#define _PAGE_READ (1<<7) /* implemented in software */
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#define _PAGE_WRITE (1<<8) /* implemented in software */
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#define _PAGE_ACCESSED (1<<9) /* implemented in software */
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#define _PAGE_MODIFIED (1<<10) /* implemented in software */
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#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
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#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1<<0)
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#define _PAGE_VALID (1<<1)
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#define _PAGE_SILENT_READ (1<<1) /* synonym */
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#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<2)
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#define _CACHE_SHIFT 3
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#define _CACHE_MASK (7<<3)
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _PAGE_PRESENT (1<<0) /* implemented in software */
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#define _PAGE_READ (1<<1) /* implemented in software */
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#define _PAGE_WRITE (1<<2) /* implemented in software */
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#define _PAGE_ACCESSED (1<<3) /* implemented in software */
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#define _PAGE_MODIFIED (1<<4) /* implemented in software */
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#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
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#define _PAGE_GLOBAL (1<<8)
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#define _PAGE_VALID (1<<9)
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#define _PAGE_SILENT_READ (1<<9) /* synonym */
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#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<10)
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#define _CACHE_UNCACHED (1<<11)
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#define _CACHE_MASK (1<<11)
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#else /* 'Normal' r4K case */
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/*
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* When using the RI/XI bit support, we have 13 bits of flags below
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* the physical address. The RI/XI bits are placed such that a SRL 5
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* can strip off the software bits, then a ROTR 2 can move the RI/XI
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* into bits [63:62]. This also limits physical address to 56 bits,
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* which is more than we need right now.
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*/
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/* implemented in software */
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#define _PAGE_PRESENT_SHIFT (0)
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
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#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
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#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
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/* implemented in software */
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#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
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#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
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/* implemented in software */
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#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
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#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
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/* implemented in software */
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#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
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#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
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/* set:pagecache unset:swap */
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#define _PAGE_FILE (_PAGE_MODIFIED)
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#ifdef CONFIG_HUGETLB_PAGE
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/* huge tlb page */
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#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
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#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
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#else
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#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
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#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
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#endif
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/* Page cannot be executed */
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#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
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#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
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/* Page cannot be read */
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#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
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#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
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#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
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#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
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#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
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#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
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/* synonym */
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#define _PAGE_SILENT_READ (_PAGE_VALID)
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/* The MIPS dirty bit */
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#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
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#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
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#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
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#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
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#define _CACHE_MASK (7 << _CACHE_SHIFT)
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#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
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#ifndef _PFN_SHIFT
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#define _PFN_SHIFT PAGE_SHIFT
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#endif
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#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
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#ifndef _PAGE_NO_READ
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#define _PAGE_NO_READ ({BUG(); 0; })
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#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
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#endif
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#ifndef _PAGE_NO_EXEC
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#define _PAGE_NO_EXEC ({BUG(); 0; })
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#endif
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#ifndef _PAGE_GLOBAL_SHIFT
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#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
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#endif
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#ifndef __ASSEMBLY__
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/*
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* pte_to_entrylo converts a page table entry (PTE) into a Mips
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* entrylo0/1 value.
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*/
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static inline uint64_t pte_to_entrylo(unsigned long pte_val)
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{
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if (kernel_uses_smartmips_rixi) {
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int sa;
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#ifdef CONFIG_32BIT
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sa = 31 - _PAGE_NO_READ_SHIFT;
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#else
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sa = 63 - _PAGE_NO_READ_SHIFT;
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#endif
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/*
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* C has no way to express that this is a DSRL
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* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
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* in the fast path this is done in assembly
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*/
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return (pte_val >> _PAGE_GLOBAL_SHIFT) |
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((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
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}
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return pte_val >> _PAGE_GLOBAL_SHIFT;
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}
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#endif
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/*
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* Cache attributes
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*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _CACHE_CACHABLE_NONCOHERENT 0
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#elif defined(CONFIG_CPU_SB1)
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/* No penalty for being coherent on the SB1, so just
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use it for "noncoherent" spaces, too. Shouldn't hurt. */
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
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#elif defined(CONFIG_CPU_RM9000)
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#define _CACHE_WT (0<<_CACHE_SHIFT)
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#define _CACHE_WTWA (1<<_CACHE_SHIFT)
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#define _CACHE_UC_B (2<<_CACHE_SHIFT)
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#define _CACHE_WB (3<<_CACHE_SHIFT)
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#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
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#define _CACHE_CWB (5<<_CACHE_SHIFT)
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#define _CACHE_UCNB (6<<_CACHE_SHIFT)
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#define _CACHE_FPC (7<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED _CACHE_UC_B
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#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
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#else
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#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
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#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
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#endif
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#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
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#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
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#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
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#endif /* _ASM_PGTABLE_BITS_H */
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