mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b7badd1d7a
As usual, this is where the bulk of our changes end up landing each merge window. The individual updates are too many to enumerate, many many platforms have seen additions of device descriptions such that they are functionally more complete (in fact, this is often the bulk of updates we see). Instead I've mostly focused on highlighting the new platforms below as they are introduced. Sometimes the introduction is of mostly a fragment, that later gets filled in on later releases, and in some cases it's near-complete platform support. The latter is more common for derivative platforms that already has similar support in-tree. Two SoCs are slight outliers from the usual range of additions. Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping in the Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at infrastructure/networking. TI updates stick out in the diff stats too, in particular because they have moved the description of their L4 on-chip interconnect to devicetree, which opens up for removal of even more of their platform-specific 'hwmod' description tables over the next few releases. SoCs: - Qualcomm QCS404 (4x Cortex-A53) - Allwinner T3 (rebranded R40) and f1c100s (armv5) - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4) - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72) New platforms: - Rockchip: Gru Scarlet (RK3188 Tablet) - Amlogic: Phicomm N1 (S905D), Libretech S805-AC - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708) - Qualcomm: QCS404 base platform and EVB - Qualcomm: Remove of Arrow SD600 - PXA: First PXA3xx DT board: Raumfeld - Aspeed: Facebook Backpack-CMM BMC - Renesas iWave G20D-Q7 (RZ/G1N) - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s) - Allwinner Emlid Neutis N5, Mapleboard MP130 - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE) - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva - VF610: Liebherr's BK4 device, ZII SCU4 AIB board - i.MX7D PICO Hobbit baseboard - i.MX7ULP EVK board - NXP LX2160AQDS and LX2160ARDB boards Other: - Coresight binding updates across the board - CPU cooling maps updates across the board -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlwqgVYPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3ybAQAKAhd7XI5oY/wgdZZmxwcX+p7sU6LXeIlpWU XsPN1c14KU0siQv/znVA5OpF+fgn9eRqfWnMoDPlvdScTq07FM2NBmOJfVJYDPJa uvsll5m+84FCYanIR//YybS0tCM0b0BHoHo2DoyIxWeAwmw7BBVslddBdNg6R7hG S9rU9rUeqfCj7HbcPLqVn0DecMtEe7R8zmDtG1CSMqrhncifmoV4gtUnbYAg0GGT cSvj/zT8A1j0oJcU2Upl/Fr+7WJ7XB9pnku91nUOSXLv5VkyctLGomKq5F7O2/Xs 2DhpH2yKwQt7S7TDiDd0jy64Of6+Xup35wEHevCeKrzGXcVRqqHwCkanLz9FdjVt yg4UrI/P1nY7h4ifZPplgigv+kA+IjRGiMrTRIEgSE5YK9U5AYkgembTWksRDikd 5EpeJcMj2tBv4SDellNNtzh6GGTPBf3GJw3P9uRuxnQY/T31N2eX0XGeRikL+Lzf 9nbQdJealmql3rCa5oFEJwSxrSaAv/ub7/294kPdEmXj8+3qUuH3hZAZOI9LSXGW GCuxsgccB2GF1M48x48/QpHgxb93okyXmndONZnU8uN8ba0zS4b8QLwvIY5rqv5Z kqD1VPBQf9kGVyzDyABRjFmGCDJcoOJf4QrzvNk9+xo8fXVk1xNtxu4MUsHvc2lS cU2RYWm/ =sFVi -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM Device-tree updates from Olof Johansson: "As usual, this is where the bulk of our changes end up landing each merge window. The individual updates are too many to enumerate, many many platforms have seen additions of device descriptions such that they are functionally more complete (in fact, this is often the bulk of updates we see). Instead I've mostly focused on highlighting the new platforms below as they are introduced. Sometimes the introduction is of mostly a fragment, that later gets filled in on later releases, and in some cases it's near-complete platform support. The latter is more common for derivative platforms that already has similar support in-tree. Two SoCs are slight outliers from the usual range of additions. Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping in the Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at infrastructure/networking. TI updates stick out in the diff stats too, in particular because they have moved the description of their L4 on-chip interconnect to devicetree, which opens up for removal of even more of their platform-specific 'hwmod' description tables over the next few releases. SoCs: - Qualcomm QCS404 (4x Cortex-A53) - Allwinner T3 (rebranded R40) and f1c100s (armv5) - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4) - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72) New platforms: - Rockchip: Gru Scarlet (RK3188 Tablet) - Amlogic: Phicomm N1 (S905D), Libretech S805-AC - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708) - Qualcomm: QCS404 base platform and EVB - Qualcomm: Remove of Arrow SD600 - PXA: First PXA3xx DT board: Raumfeld - Aspeed: Facebook Backpack-CMM BMC - Renesas iWave G20D-Q7 (RZ/G1N) - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s) - Allwinner Emlid Neutis N5, Mapleboard MP130 - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE) - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva - VF610: Liebherr's BK4 device, ZII SCU4 AIB board - i.MX7D PICO Hobbit baseboard - i.MX7ULP EVK board - NXP LX2160AQDS and LX2160ARDB boards Other: - Coresight binding updates across the board - CPU cooling maps updates across the board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits) ARM: dts: suniv: Fix improper bindings include patch ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node ARM: dts: suniv: Fix improper bindings include patch arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller arm64: dts: Remove unused properties from FSL QSPI driver nodes ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes ARM: dts: Remove unused properties from FSL QSPI driver nodes arm64: dts: ti: k3-am654: Enable main domain McSPI0 arm64: dts: ti: k3-am654: Add McSPI DT nodes arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM arm64: dts: ti: k3-am65-main: Add ECAP PWM node arm64: dts: ti: k3-am654-base-board: Add I2C nodes arm64: dts: ti: am654-base-board: Add pinmux for main uart0 arm64: dts: ti: k3-am65: Add pinctrl regions dt-bindings: pinctrl: k3: Introduce pinmux definitions ARM: dts: exynos: Specify I2S assigned clocks in proper node ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2 ...
574 lines
13 KiB
Plaintext
574 lines
13 KiB
Plaintext
/*
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* Copyright Altera Corporation (C) 2015. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/stratix10-clock.h>
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/ {
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compatible = "altr,socfpga-stratix10";
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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service_reserved: svcbuffer@0 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x0 0x0 0x1000000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 120 8>,
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<0 121 8>,
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<0 122 8>,
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<0 123 8>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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interrupt-parent = <&intc>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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intc: intc@fffc1000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0xfffc1000 0x0 0x1000>,
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<0x0 0xfffc2000 0x0 0x2000>,
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<0x0 0xfffc4000 0x0 0x2000>,
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<0x0 0xfffc6000 0x0 0x2000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges = <0 0 0 0xffffffff>;
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base_fpga_region {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "fpga-region";
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fpga-mgr = <&fpga_mgr>;
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};
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clkmgr: clock-controller@ffd10000 {
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compatible = "intel,stratix10-clkmgr";
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reg = <0xffd10000 0x1000>;
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#clock-cells = <1>;
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};
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clocks {
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cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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cb_intosc_ls_clk: cb-intosc-ls-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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f2s_free_clk: f2s-free-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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qspi_clk: qspi-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff800000 0x2000>;
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interrupts = <0 90 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
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clock-names = "stmmaceth";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff802000 0x2000>;
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interrupts = <0 91 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
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clock-names = "stmmaceth";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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status = "disabled";
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff804000 0x2000>;
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interrupts = <0 92 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
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clock-names = "stmmaceth";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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status = "disabled";
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};
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gpio0: gpio@ffc03200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03200 0x100>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 110 4>;
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};
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};
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gpio1: gpio@ffc03300 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03300 0x100>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 111 4>;
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};
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};
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i2c0: i2c@ffc02800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02800 0x100>;
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interrupts = <0 103 4>;
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resets = <&rst I2C0_RESET>;
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clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
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status = "disabled";
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};
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i2c1: i2c@ffc02900 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02900 0x100>;
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interrupts = <0 104 4>;
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resets = <&rst I2C1_RESET>;
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clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
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status = "disabled";
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};
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i2c2: i2c@ffc02a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02a00 0x100>;
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interrupts = <0 105 4>;
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resets = <&rst I2C2_RESET>;
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clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
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status = "disabled";
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};
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i2c3: i2c@ffc02b00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02b00 0x100>;
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interrupts = <0 106 4>;
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resets = <&rst I2C3_RESET>;
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clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
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status = "disabled";
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};
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i2c4: i2c@ffc02c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02c00 0x100>;
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interrupts = <0 107 4>;
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resets = <&rst I2C4_RESET>;
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clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
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status = "disabled";
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};
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mmc: dwmmc0@ff808000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff808000 0x1000>;
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interrupts = <0 96 4>;
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fifo-depth = <0x400>;
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resets = <&rst SDMMC_RESET>;
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reset-names = "reset";
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clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
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<&clkmgr STRATIX10_SDMMC_CLK>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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ocram: sram@ffe00000 {
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compatible = "mmio-sram";
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reg = <0xffe00000 0x100000>;
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};
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pdma: pdma@ffda0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffda0000 0x1000>;
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interrupts = <0 81 4>,
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<0 82 4>,
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<0 83 4>,
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<0 84 4>,
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<0 85 4>,
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<0 86 4>,
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<0 87 4>,
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<0 88 4>,
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<0 89 4>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
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clock-names = "apb_pclk";
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};
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rst: rstmgr@ffd11000 {
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#reset-cells = <1>;
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compatible = "altr,stratix10-rst-mgr";
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reg = <0xffd11000 0x1000>;
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};
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spi0: spi@ffda4000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda4000 0x1000>;
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interrupts = <0 99 4>;
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resets = <&rst SPIM0_RESET>;
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reg-io-width = <4>;
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num-cs = <4>;
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clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
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status = "disabled";
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|
};
|
|
|
|
spi1: spi@ffda5000 {
|
|
compatible = "snps,dw-apb-ssi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xffda5000 0x1000>;
|
|
interrupts = <0 100 4>;
|
|
resets = <&rst SPIM1_RESET>;
|
|
reg-io-width = <4>;
|
|
num-cs = <4>;
|
|
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sysmgr: sysmgr@ffd12000 {
|
|
compatible = "altr,sys-mgr", "syscon";
|
|
reg = <0xffd12000 0x228>;
|
|
};
|
|
|
|
/* Local timer */
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 13 0xf08>,
|
|
<1 14 0xf08>,
|
|
<1 11 0xf08>,
|
|
<1 10 0xf08>;
|
|
};
|
|
|
|
timer0: timer0@ffc03000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 113 4>;
|
|
reg = <0xffc03000 0x100>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
clock-names = "timer";
|
|
};
|
|
|
|
timer1: timer1@ffc03100 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 114 4>;
|
|
reg = <0xffc03100 0x100>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
clock-names = "timer";
|
|
};
|
|
|
|
timer2: timer2@ffd00000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 115 4>;
|
|
reg = <0xffd00000 0x100>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
clock-names = "timer";
|
|
};
|
|
|
|
timer3: timer3@ffd00100 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 116 4>;
|
|
reg = <0xffd00100 0x100>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
clock-names = "timer";
|
|
};
|
|
|
|
uart0: serial0@ffc02000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc02000 0x100>;
|
|
interrupts = <0 108 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
resets = <&rst UART0_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial1@ffc02100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc02100 0x100>;
|
|
interrupts = <0 109 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
resets = <&rst UART1_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy0: usbphy@0 {
|
|
#phy-cells = <0>;
|
|
compatible = "usb-nop-xceiv";
|
|
status = "okay";
|
|
};
|
|
|
|
usb0: usb@ffb00000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0xffb00000 0x40000>;
|
|
interrupts = <0 93 4>;
|
|
phys = <&usbphy0>;
|
|
phy-names = "usb2-phy";
|
|
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
|
|
reset-names = "dwc2", "dwc2-ecc";
|
|
clocks = <&clkmgr STRATIX10_USB_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: usb@ffb40000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0xffb40000 0x40000>;
|
|
interrupts = <0 94 4>;
|
|
phys = <&usbphy0>;
|
|
phy-names = "usb2-phy";
|
|
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
|
|
reset-names = "dwc2", "dwc2-ecc";
|
|
clocks = <&clkmgr STRATIX10_USB_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog0: watchdog@ffd00200 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00200 0x100>;
|
|
interrupts = <0 117 4>;
|
|
resets = <&rst WATCHDOG0_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog1: watchdog@ffd00300 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00300 0x100>;
|
|
interrupts = <0 118 4>;
|
|
resets = <&rst WATCHDOG1_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog2: watchdog@ffd00400 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00400 0x100>;
|
|
interrupts = <0 125 4>;
|
|
resets = <&rst WATCHDOG2_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog3: watchdog@ffd00500 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00500 0x100>;
|
|
interrupts = <0 126 4>;
|
|
resets = <&rst WATCHDOG3_RESET>;
|
|
clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdr: sdr@f8011100 {
|
|
compatible = "altr,sdr-ctl", "syscon";
|
|
reg = <0xf8011100 0xc0>;
|
|
};
|
|
|
|
eccmgr {
|
|
compatible = "altr,socfpga-a10-ecc-manager";
|
|
altr,sysmgr-syscon = <&sysmgr>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupts = <0 15 4>, <0 95 4>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ranges;
|
|
|
|
sdramedac {
|
|
compatible = "altr,sdram-edac-s10";
|
|
altr,sdr-syscon = <&sdr>;
|
|
interrupts = <16 4>, <48 4>;
|
|
};
|
|
|
|
usb0-ecc@ff8c4000 {
|
|
compatible = "altr,socfpga-usb-ecc";
|
|
reg = <0xff8c4000 0x100>;
|
|
altr,ecc-parent = <&usb0>;
|
|
interrupts = <2 4>,
|
|
<34 4>;
|
|
};
|
|
|
|
emac0-rx-ecc@ff8c0000 {
|
|
compatible = "altr,socfpga-eth-mac-ecc";
|
|
reg = <0xff8c0000 0x100>;
|
|
altr,ecc-parent = <&gmac0>;
|
|
interrupts = <4 4>,
|
|
<36 4>;
|
|
};
|
|
|
|
emac0-tx-ecc@ff8c0400 {
|
|
compatible = "altr,socfpga-eth-mac-ecc";
|
|
reg = <0xff8c0400 0x100>;
|
|
altr,ecc-parent = <&gmac0>;
|
|
interrupts = <5 4>,
|
|
<37 4>;
|
|
};
|
|
|
|
};
|
|
|
|
qspi: spi@ff8d2000 {
|
|
compatible = "cdns,qspi-nor";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xff8d2000 0x100>,
|
|
<0xff900000 0x100000>;
|
|
interrupts = <0 3 4>;
|
|
cdns,fifo-depth = <128>;
|
|
cdns,fifo-width = <4>;
|
|
cdns,trigger-address = <0x00000000>;
|
|
clocks = <&qspi_clk>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
firmware {
|
|
svc {
|
|
compatible = "intel,stratix10-svc";
|
|
method = "smc";
|
|
memory-region = <&service_reserved>;
|
|
|
|
fpga_mgr: fpga-mgr {
|
|
compatible = "intel,stratix10-soc-fpga-mgr";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|