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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dc86e88c2b
sparc64, i386 and x86_64 have support for a special data section dedicated to rarely updated data that is frequently read. The section was created to avoid false sharing of those rarely read data with frequently written kernel data. This patch creates such a data section for ia64 and will group rarely written data into this section. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
#ifndef __LINUX_CACHE_H
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#define __LINUX_CACHE_H
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#include <linux/kernel.h>
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#include <linux/config.h>
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#include <asm/cache.h>
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#ifndef L1_CACHE_ALIGN
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#define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES)
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#endif
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#ifndef SMP_CACHE_BYTES
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif
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#if defined(CONFIG_X86) || defined(CONFIG_SPARC64) || defined(CONFIG_IA64)
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#define __read_mostly __attribute__((__section__(".data.read_mostly")))
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#else
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#define __read_mostly
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#endif
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#ifndef ____cacheline_aligned
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#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
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#endif
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#ifndef ____cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define ____cacheline_aligned_in_smp ____cacheline_aligned
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#else
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#define ____cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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#ifndef __cacheline_aligned
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#define __cacheline_aligned \
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__attribute__((__aligned__(SMP_CACHE_BYTES), \
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__section__(".data.cacheline_aligned")))
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#endif /* __cacheline_aligned */
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#ifndef __cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define __cacheline_aligned_in_smp __cacheline_aligned
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#else
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#define __cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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#if !defined(____cacheline_maxaligned_in_smp)
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#if defined(CONFIG_SMP)
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#define ____cacheline_maxaligned_in_smp \
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__attribute__((__aligned__(1 << (L1_CACHE_SHIFT_MAX))))
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#else
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#define ____cacheline_maxaligned_in_smp
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#endif
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#endif
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#endif /* __LINUX_CACHE_H */
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