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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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df09df6f9a
The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422-cpus.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Chanho Park <parkch98@gmail.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
82 lines
1.8 KiB
Plaintext
82 lines
1.8 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5422 SoC cpu device tree source
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
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* EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
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* from Cortex-A15 core.
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*
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* EXYNOS5422 based board files can include this file to provide cpu ordering
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* which could boot a cortex-a7 from cpu0.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cpu0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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&cpu4 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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&cpu5 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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&cpu6 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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&cpu7 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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