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97a5e98c1b
The field contains more bits than just the one to indicate whether scsi prefetch should be turned on. Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
399 lines
10 KiB
C
399 lines
10 KiB
C
/*
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* Disk Array driver for HP Smart Array SAS controllers
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* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Questions/Comments/Bugfixes to iss_storagedev@hp.com
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*
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*/
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#ifndef HPSA_CMD_H
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#define HPSA_CMD_H
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/* general boundary defintions */
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#define SENSEINFOBYTES 32 /* may vary between hbas */
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#define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
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#define HPSA_SG_CHAIN 0x80000000
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#define MAXREPLYQS 256
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/* Command Status value */
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#define CMD_SUCCESS 0x0000
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#define CMD_TARGET_STATUS 0x0001
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#define CMD_DATA_UNDERRUN 0x0002
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#define CMD_DATA_OVERRUN 0x0003
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#define CMD_INVALID 0x0004
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#define CMD_PROTOCOL_ERR 0x0005
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#define CMD_HARDWARE_ERR 0x0006
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#define CMD_CONNECTION_LOST 0x0007
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#define CMD_ABORTED 0x0008
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#define CMD_ABORT_FAILED 0x0009
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#define CMD_UNSOLICITED_ABORT 0x000A
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#define CMD_TIMEOUT 0x000B
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#define CMD_UNABORTABLE 0x000C
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/* Unit Attentions ASC's as defined for the MSA2012sa */
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#define POWER_OR_RESET 0x29
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#define STATE_CHANGED 0x2a
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#define UNIT_ATTENTION_CLEARED 0x2f
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#define LUN_FAILED 0x3e
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#define REPORT_LUNS_CHANGED 0x3f
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/* Unit Attentions ASCQ's as defined for the MSA2012sa */
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/* These ASCQ's defined for ASC = POWER_OR_RESET */
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#define POWER_ON_RESET 0x00
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#define POWER_ON_REBOOT 0x01
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#define SCSI_BUS_RESET 0x02
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#define MSA_TARGET_RESET 0x03
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#define CONTROLLER_FAILOVER 0x04
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#define TRANSCEIVER_SE 0x05
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#define TRANSCEIVER_LVD 0x06
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/* These ASCQ's defined for ASC = STATE_CHANGED */
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#define RESERVATION_PREEMPTED 0x03
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#define ASYM_ACCESS_CHANGED 0x06
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#define LUN_CAPACITY_CHANGED 0x09
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/* transfer direction */
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#define XFER_NONE 0x00
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#define XFER_WRITE 0x01
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#define XFER_READ 0x02
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#define XFER_RSVD 0x03
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/* task attribute */
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#define ATTR_UNTAGGED 0x00
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#define ATTR_SIMPLE 0x04
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#define ATTR_HEADOFQUEUE 0x05
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#define ATTR_ORDERED 0x06
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#define ATTR_ACA 0x07
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/* cdb type */
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#define TYPE_CMD 0x00
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#define TYPE_MSG 0x01
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/* Message Types */
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#define HPSA_TASK_MANAGEMENT 0x00
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#define HPSA_RESET 0x01
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#define HPSA_SCAN 0x02
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#define HPSA_NOOP 0x03
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#define HPSA_CTLR_RESET_TYPE 0x00
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#define HPSA_BUS_RESET_TYPE 0x01
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#define HPSA_TARGET_RESET_TYPE 0x03
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#define HPSA_LUN_RESET_TYPE 0x04
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#define HPSA_NEXUS_RESET_TYPE 0x05
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/* Task Management Functions */
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#define HPSA_TMF_ABORT_TASK 0x00
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#define HPSA_TMF_ABORT_TASK_SET 0x01
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#define HPSA_TMF_CLEAR_ACA 0x02
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#define HPSA_TMF_CLEAR_TASK_SET 0x03
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#define HPSA_TMF_QUERY_TASK 0x04
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#define HPSA_TMF_QUERY_TASK_SET 0x05
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#define HPSA_TMF_QUERY_ASYNCEVENT 0x06
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/* config space register offsets */
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#define CFG_VENDORID 0x00
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#define CFG_DEVICEID 0x02
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#define CFG_I2OBAR 0x10
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#define CFG_MEM1BAR 0x14
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/* i2o space register offsets */
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#define I2O_IBDB_SET 0x20
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#define I2O_IBDB_CLEAR 0x70
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#define I2O_INT_STATUS 0x30
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#define I2O_INT_MASK 0x34
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#define I2O_IBPOST_Q 0x40
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#define I2O_OBPOST_Q 0x44
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#define I2O_DMA1_CFG 0x214
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/* Configuration Table */
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#define CFGTBL_ChangeReq 0x00000001l
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#define CFGTBL_AccCmds 0x00000001l
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#define DOORBELL_CTLR_RESET 0x00000004l
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#define DOORBELL_CTLR_RESET2 0x00000020l
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#define CFGTBL_Trans_Simple 0x00000002l
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#define CFGTBL_Trans_Performant 0x00000004l
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#define CFGTBL_Trans_use_short_tags 0x20000000l
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#define CFGTBL_Trans_enable_directed_msix (1 << 30)
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#define CFGTBL_BusType_Ultra2 0x00000001l
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#define CFGTBL_BusType_Ultra3 0x00000002l
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#define CFGTBL_BusType_Fibre1G 0x00000100l
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#define CFGTBL_BusType_Fibre2G 0x00000200l
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struct vals32 {
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u32 lower;
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u32 upper;
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};
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union u64bit {
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struct vals32 val32;
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u64 val;
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};
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/* FIXME this is a per controller value (barf!) */
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#define HPSA_MAX_LUN 1024
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#define HPSA_MAX_PHYS_LUN 1024
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#define MAX_EXT_TARGETS 32
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#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
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MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
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/* SCSI-3 Commands */
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#pragma pack(1)
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#define HPSA_INQUIRY 0x12
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struct InquiryData {
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u8 data_byte[36];
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};
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#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
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#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
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struct ReportLUNdata {
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u8 LUNListLength[4];
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u32 reserved;
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u8 LUN[HPSA_MAX_LUN][8];
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};
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struct ReportExtendedLUNdata {
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u8 LUNListLength[4];
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u8 extended_response_flag;
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u8 reserved[3];
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u8 LUN[HPSA_MAX_LUN][24];
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};
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struct SenseSubsystem_info {
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u8 reserved[36];
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u8 portname[8];
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u8 reserved1[1108];
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};
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/* BMIC commands */
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#define BMIC_READ 0x26
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#define BMIC_WRITE 0x27
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#define BMIC_CACHE_FLUSH 0xc2
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#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
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#define BMIC_FLASH_FIRMWARE 0xF7
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/* Command List Structure */
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union SCSI3Addr {
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struct {
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u8 Dev;
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u8 Bus:6;
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u8 Mode:2; /* b00 */
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} PeripDev;
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struct {
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u8 DevLSB;
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u8 DevMSB:6;
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u8 Mode:2; /* b01 */
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} LogDev;
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struct {
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u8 Dev:5;
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u8 Bus:3;
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u8 Targ:6;
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u8 Mode:2; /* b10 */
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} LogUnit;
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};
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struct PhysDevAddr {
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u32 TargetId:24;
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u32 Bus:6;
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u32 Mode:2;
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/* 2 level target device addr */
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union SCSI3Addr Target[2];
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};
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struct LogDevAddr {
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u32 VolId:30;
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u32 Mode:2;
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u8 reserved[4];
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};
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union LUNAddr {
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u8 LunAddrBytes[8];
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union SCSI3Addr SCSI3Lun[4];
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struct PhysDevAddr PhysDev;
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struct LogDevAddr LogDev;
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};
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struct CommandListHeader {
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u8 ReplyQueue;
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u8 SGList;
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u16 SGTotal;
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struct vals32 Tag;
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union LUNAddr LUN;
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};
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struct RequestBlock {
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u8 CDBLen;
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struct {
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u8 Type:3;
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u8 Attribute:3;
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u8 Direction:2;
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} Type;
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u16 Timeout;
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u8 CDB[16];
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};
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struct ErrDescriptor {
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struct vals32 Addr;
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u32 Len;
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};
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struct SGDescriptor {
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struct vals32 Addr;
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u32 Len;
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u32 Ext;
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};
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union MoreErrInfo {
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struct {
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u8 Reserved[3];
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u8 Type;
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u32 ErrorInfo;
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} Common_Info;
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struct {
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u8 Reserved[2];
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u8 offense_size; /* size of offending entry */
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u8 offense_num; /* byte # of offense 0-base */
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u32 offense_value;
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} Invalid_Cmd;
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};
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struct ErrorInfo {
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u8 ScsiStatus;
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u8 SenseLen;
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u16 CommandStatus;
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u32 ResidualCnt;
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union MoreErrInfo MoreErrInfo;
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u8 SenseInfo[SENSEINFOBYTES];
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};
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/* Command types */
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#define CMD_IOCTL_PEND 0x01
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#define CMD_SCSI 0x03
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#define DIRECT_LOOKUP_SHIFT 5
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#define DIRECT_LOOKUP_BIT 0x10
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#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
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#define HPSA_ERROR_BIT 0x02
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struct ctlr_info; /* defined in hpsa.h */
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/* The size of this structure needs to be divisible by 32
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* on all architectures because low 5 bits of the addresses
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* are used as follows:
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*
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* bit 0: to device, used to indicate "performant mode" command
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* from device, indidcates error status.
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* bit 1-3: to device, indicates block fetch table entry for
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* reducing DMA in fetching commands from host memory.
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* bit 4: used to indicate whether tag is "direct lookup" (index),
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* or a bus address.
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*/
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struct CommandList {
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struct CommandListHeader Header;
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struct RequestBlock Request;
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struct ErrDescriptor ErrDesc;
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struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
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/* information associated with the command */
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u32 busaddr; /* physical addr of this record */
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struct ErrorInfo *err_info; /* pointer to the allocated mem */
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struct ctlr_info *h;
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int cmd_type;
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long cmdindex;
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struct list_head list;
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struct request *rq;
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struct completion *waiting;
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void *scsi_cmd;
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/* on 64 bit architectures, to get this to be 32-byte-aligned
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* it so happens we need PAD_64 bytes of padding, on 32 bit systems,
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* we need PAD_32 bytes of padding (see below). This does that.
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* If it happens that 64 bit and 32 bit systems need different
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* padding, PAD_32 and PAD_64 can be set independently, and.
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* the code below will do the right thing.
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*/
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#define IS_32_BIT ((8 - sizeof(long))/4)
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#define IS_64_BIT (!IS_32_BIT)
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#define PAD_32 (4)
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#define PAD_64 (4)
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#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
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u8 pad[COMMANDLIST_PAD];
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};
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/* Configuration Table Structure */
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struct HostWrite {
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u32 TransportRequest;
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u32 Reserved;
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u32 CoalIntDelay;
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u32 CoalIntCount;
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};
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#define SIMPLE_MODE 0x02
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#define PERFORMANT_MODE 0x04
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#define MEMQ_MODE 0x08
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struct CfgTable {
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u8 Signature[4];
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u32 SpecValence;
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u32 TransportSupport;
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u32 TransportActive;
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struct HostWrite HostWrite;
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u32 CmdsOutMax;
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u32 BusTypes;
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u32 TransMethodOffset;
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u8 ServerName[16];
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u32 HeartBeat;
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u32 driver_support;
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#define ENABLE_SCSI_PREFETCH 0x100
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u32 MaxScatterGatherElements;
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u32 MaxLogicalUnits;
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u32 MaxPhysicalDevices;
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u32 MaxPhysicalDrivesPerLogicalUnit;
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u32 MaxPerformantModeCommands;
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u32 MaxBlockFetch;
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u32 PowerConservationSupport;
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u32 PowerConservationEnable;
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u32 TMFSupportFlags;
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u8 TMFTagMask[8];
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u8 reserved[0x78 - 0x70];
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u32 misc_fw_support; /* offset 0x78 */
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#define MISC_FW_DOORBELL_RESET (0x02)
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#define MISC_FW_DOORBELL_RESET2 (0x010)
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u8 driver_version[32];
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};
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#define NUM_BLOCKFETCH_ENTRIES 8
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struct TransTable_struct {
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u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
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u32 RepQSize;
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u32 RepQCount;
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u32 RepQCtrAddrLow32;
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u32 RepQCtrAddrHigh32;
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#define MAX_REPLY_QUEUES 8
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struct vals32 RepQAddr[MAX_REPLY_QUEUES];
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};
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struct hpsa_pci_info {
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unsigned char bus;
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unsigned char dev_fn;
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unsigned short domain;
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u32 board_id;
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};
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#pragma pack()
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#endif /* HPSA_CMD_H */
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