mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 15:46:54 +07:00
1849f800fb
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device
support for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H
with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module
plus board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600
and the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation
of the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards
are added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC platforms
from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much
more useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device support
for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with
10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus
board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and
the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation of
the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are
added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC
platforms from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much more
useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits)
ARM: dts: socfpga: set the i2c frequency
ARM: dts: socfpga: Add second ethernet alias to VINING FPGA
ARM: dts: socfpga: Drop LED node from VINING FPGA
ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA
ARM: dts: socfpga: Enable QSPI support on VINING FPGA
ARM: dts: socfpga: Fix the ethernet clock phandle
ARM: pxa: Use - instead of @ for DT OPP entries
ARM: dts: owl-s500: Add SPS node
ARM: dts: owl-s500: Set CPU enable-method
dt-bindings: arm: cpus: Add S500 enable-method
ARM: dts: Add Actions Semi S500 and LeMaker Guitar
dt-bindings: arm: Document Actions Semi S900
dt-bindings: timer: Document Owl timer
ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes
dt-bindings: arm: Document Actions Semi S500
dt-bindings: Add vendor prefix for Actions Semi
ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM
ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango)
ARM: dts: armada-385-linksys: fixup button node names
ARM: dts: armada-385-linksys: group pins in pinctrl
...
645 lines
17 KiB
Plaintext
645 lines
17 KiB
Plaintext
/*
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun8i-h3-ccu.h>
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#include <dt-bindings/reset/sun8i-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun8i-h3-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun8i-h3-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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/* compatible and clocks are in per SoC .dtsi file */
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reg = <0x01c0f000 0x1000>;
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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/* compatible and clocks are in per SoC .dtsi file */
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reg = <0x01c10000 0x1000>;
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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/* compatible and clocks are in per SoC .dtsi file */
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reg = <0x01c11000 0x1000>;
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@01c19000 {
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compatible = "allwinner,sun8i-h3-musb";
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reg = <0x01c19000 0x400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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status = "disabled";
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun8i-h3-usb-phy";
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reg = <0x01c19400 0x2c>,
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<0x01c1a800 0x4>,
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<0x01c1b800 0x4>,
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<0x01c1c800 0x4>,
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<0x01c1d800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu1",
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"pmu2",
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"pmu3";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>,
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<&ccu CLK_USB_PHY2>,
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<&ccu CLK_USB_PHY3>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"usb2_phy",
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"usb3_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>,
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<&ccu RST_USB_PHY2>,
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<&ccu RST_USB_PHY3>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset",
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"usb3_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
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resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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status = "disabled";
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};
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ohci0: usb@01c1a400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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status = "disabled";
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
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resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci2: usb@01c1c000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1c000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
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resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci2: usb@01c1c400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
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<&ccu CLK_USB_OHCI2>;
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resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci3: usb@01c1d000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1d000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
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resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci3: usb@01c1d400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1d400 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
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<&ccu CLK_USB_OHCI3>;
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resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@01c20000 {
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/* compatible is in per SoC .dtsi file */
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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/* compatible is in per SoC .dtsi file */
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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emac_rgmii_pins: emac0 {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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"PD12", "PD13", "PD15", "PD16", "PD17";
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function = "emac";
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drive-strength = <40>;
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};
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i2c0_pins: i2c0 {
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pins = "PA11", "PA12";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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pins = "PA18", "PA19";
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function = "i2c1";
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};
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i2c2_pins: i2c2 {
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pins = "PE12", "PE13";
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function = "i2c2";
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};
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mmc0_pins_a: mmc0@0 {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc0_cd_pin: mmc0_cd_pin@0 {
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pins = "PF6";
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function = "gpio_in";
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bias-pull-up;
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};
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mmc1_pins_a: mmc1@0 {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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|
|
mmc2_8bit_pins: mmc2_8bit {
|
|
pins = "PC5", "PC6", "PC8",
|
|
"PC9", "PC10", "PC11",
|
|
"PC12", "PC13", "PC14",
|
|
"PC15", "PC16";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
spdif_tx_pins_a: spdif@0 {
|
|
pins = "PA17";
|
|
function = "spdif";
|
|
};
|
|
|
|
spi0_pins: spi0 {
|
|
pins = "PC0", "PC1", "PC2", "PC3";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi1_pins: spi1 {
|
|
pins = "PA15", "PA16", "PA14", "PA13";
|
|
function = "spi1";
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
pins = "PA4", "PA5";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart1_pins: uart1 {
|
|
pins = "PG6", "PG7";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart1_rts_cts_pins: uart1_rts_cts {
|
|
pins = "PG8", "PG9";
|
|
function = "uart1";
|
|
};
|
|
|
|
uart2_pins: uart2 {
|
|
pins = "PA0", "PA1";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart3_pins: uart3 {
|
|
pins = "PA13", "PA14";
|
|
function = "uart3";
|
|
};
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
emac: ethernet@1c30000 {
|
|
compatible = "allwinner,sun8i-h3-emac";
|
|
syscon = <&syscon>;
|
|
reg = <0x01c30000 0x104>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
resets = <&ccu RST_BUS_EMAC>;
|
|
reset-names = "stmmaceth";
|
|
clocks = <&ccu CLK_BUS_EMAC>;
|
|
clock-names = "stmmaceth";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
int_mii_phy: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <1>;
|
|
clocks = <&ccu CLK_BUS_EPHY>;
|
|
resets = <&ccu RST_BUS_EPHY>;
|
|
};
|
|
};
|
|
};
|
|
|
|
spi0: spi@01c68000 {
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 23>, <&dma 23>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_pins>;
|
|
resets = <&ccu RST_BUS_SPI0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi1: spi@01c69000 {
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
reg = <0x01c69000 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 24>, <&dma 24>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_pins>;
|
|
resets = <&ccu RST_BUS_SPI1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
wdt0: watchdog@01c20ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x01c20ca0 0x20>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spdif: spdif@01c21000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun8i-h3-spdif";
|
|
reg = <0x01c21000 0x400>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
|
|
resets = <&ccu RST_BUS_SPDIF>;
|
|
clock-names = "apb", "spdif";
|
|
dmas = <&dma 2>;
|
|
dma-names = "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@01c21400 {
|
|
compatible = "allwinner,sun8i-h3-pwm";
|
|
reg = <0x01c21400 0x8>;
|
|
clocks = <&osc24M>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@01c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun8i-h3-codec";
|
|
reg = <0x01c22c00 0x400>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
|
|
clock-names = "apb", "codec";
|
|
resets = <&ccu RST_BUS_CODEC>;
|
|
dmas = <&dma 15>, <&dma 15>;
|
|
dma-names = "rx", "tx";
|
|
allwinner,codec-analog-controls = <&codec_analog>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x2000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_ccu: clock@1f01400 {
|
|
compatible = "allwinner,sun8i-h3-r-ccu";
|
|
reg = <0x01f01400 0x100>;
|
|
clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
|
<&ccu 9>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
codec_analog: codec-analog@01f015c0 {
|
|
compatible = "allwinner,sun8i-h3-codec-analog";
|
|
reg = <0x01f015c0 0x4>;
|
|
};
|
|
|
|
ir: ir@01f02000 {
|
|
compatible = "allwinner,sun5i-a13-ir";
|
|
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
|
|
clock-names = "apb", "ir";
|
|
resets = <&r_ccu RST_APB0_IR>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01f02000 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@01f02c00 {
|
|
compatible = "allwinner,sun8i-h3-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
ir_pins_a: ir@0 {
|
|
pins = "PL11";
|
|
function = "s_cir_rx";
|
|
};
|
|
};
|
|
};
|
|
};
|