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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3c22ba5243
Update and cleanup POWER9 PMU events. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Cc: Anton Blanchard <anton@au1.ibm.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
32 lines
1.1 KiB
JSON
32 lines
1.1 KiB
JSON
[
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{,
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"EventCode": "0x1415A",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
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},
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{,
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"EventCode": "0x10058",
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"EventName": "PM_MEM_LOC_THRESH_IFU",
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"BriefDescription": "Local Memory above threshold for IFU speculation control"
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},
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{,
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"EventCode": "0x2D028",
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"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
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"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
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},
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{,
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"EventCode": "0x30012",
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"EventName": "PM_FLUSH_COMPLETION",
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"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
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},
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{,
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"EventCode": "0x2D154",
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"EventName": "PM_MRK_DERAT_MISS_64K",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
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},
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{,
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"EventCode": "0x4016E",
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"EventName": "PM_THRESH_NOT_MET",
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"BriefDescription": "Threshold counter did not meet threshold"
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}
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] |