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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d27a7e299d
A new call to SCU intel_scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
694 lines
19 KiB
C
694 lines
19 KiB
C
/*
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* intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
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*
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* (C) Copyright 2008-2010,2015 Intel Corporation
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* Author: Sreedhara DS (sreedhara.ds@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* SCU running in ARC processor communicates with other entity running in IA
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* core through IPC mechanism which in turn messaging between IA core ad SCU.
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* SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
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* SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
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* IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
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* along with other APIs.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/pm.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/sfi.h>
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#include <asm/intel-mid.h>
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#include <asm/intel_scu_ipc.h>
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/* IPC defines the following message types */
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#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
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#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
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#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
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#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
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#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
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/* Command id associated with message IPCMSG_PCNTRL */
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#define IPC_CMD_PCNTRL_W 0 /* Register write */
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#define IPC_CMD_PCNTRL_R 1 /* Register read */
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#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
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/*
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* IPC register summary
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*
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* IPC register blocks are memory mapped at fixed address of PCI BAR 0.
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* To read or write information to the SCU, driver writes to IPC-1 memory
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* mapped registers. The following is the IPC mechanism
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*
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* 1. IA core cDMI interface claims this transaction and converts it to a
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* Transaction Layer Packet (TLP) message which is sent across the cDMI.
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*
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* 2. South Complex cDMI block receives this message and writes it to
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* the IPC-1 register block, causing an interrupt to the SCU
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*
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* 3. SCU firmware decodes this interrupt and IPC message and the appropriate
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* message handler is called within firmware.
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*/
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#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
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#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
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#define IPC_IOC 0x100 /* IPC command register IOC bit */
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#define PCI_DEVICE_ID_LINCROFT 0x082a
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#define PCI_DEVICE_ID_PENWELL 0x080e
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#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
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#define PCI_DEVICE_ID_TANGIER 0x11a0
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/* intel scu ipc driver data */
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struct intel_scu_ipc_pdata_t {
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u32 i2c_base;
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u32 i2c_len;
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u8 irq_mode;
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};
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static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
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.i2c_base = 0xff12b000,
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.i2c_len = 0x10,
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.irq_mode = 0,
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};
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/* Penwell and Cloverview */
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static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
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.i2c_base = 0xff12b000,
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.i2c_len = 0x10,
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.irq_mode = 1,
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};
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static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
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.i2c_base = 0xff00d000,
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.i2c_len = 0x10,
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.irq_mode = 0,
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};
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struct intel_scu_ipc_dev {
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struct device *dev;
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void __iomem *ipc_base;
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void __iomem *i2c_base;
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struct completion cmd_complete;
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u8 irq_mode;
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};
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static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
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/*
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* IPC Read Buffer (Read Only):
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* 16 byte buffer for receiving data from SCU, if IPC command
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* processing results in response data
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*/
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#define IPC_READ_BUFFER 0x90
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#define IPC_I2C_CNTRL_ADDR 0
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#define I2C_DATA_ADDR 0x04
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static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
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/*
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* Send ipc command
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* Command Register (Write Only):
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* A write to this register results in an interrupt to the SCU core processor
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* Format:
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* |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
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*/
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static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
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{
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if (scu->irq_mode) {
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reinit_completion(&scu->cmd_complete);
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writel(cmd | IPC_IOC, scu->ipc_base);
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}
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writel(cmd, scu->ipc_base);
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}
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/*
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* Write ipc data
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* IPC Write Buffer (Write Only):
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* 16-byte buffer for sending data associated with IPC command to
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* SCU. Size of the data is specified in the IPC_COMMAND_REG register
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*/
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static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
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{
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writel(data, scu->ipc_base + 0x80 + offset);
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}
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/*
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* Status Register (Read Only):
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* Driver will read this register to get the ready/busy status of the IPC
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* block and error status of the IPC command that was just processed by SCU
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* Format:
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* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
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*/
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static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
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{
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return __raw_readl(scu->ipc_base + 0x04);
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}
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/* Read ipc byte data */
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static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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/* Read ipc u32 data */
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static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
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{
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return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
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}
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/* Wait till scu status is busy */
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static inline int busy_loop(struct intel_scu_ipc_dev *scu)
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{
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u32 status = ipc_read_status(scu);
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u32 loop_count = 100000;
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/* break if scu doesn't reset busy bit after huge retry */
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while ((status & BIT(0)) && --loop_count) {
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udelay(1); /* scu processing time is in few u secods */
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status = ipc_read_status(scu);
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}
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if (status & BIT(0)) {
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dev_err(scu->dev, "IPC timed out");
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return -ETIMEDOUT;
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}
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if (status & BIT(1))
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return -EIO;
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return 0;
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}
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/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
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static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
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{
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int status;
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if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
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dev_err(scu->dev, "IPC timed out\n");
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return -ETIMEDOUT;
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}
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status = ipc_read_status(scu);
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if (status & BIT(1))
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return -EIO;
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return 0;
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}
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static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
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{
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return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
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}
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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int nc;
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u32 offset = 0;
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int err;
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u8 cbuf[IPC_WWBUF_SIZE];
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u32 *wbuf = (u32 *)&cbuf;
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memset(cbuf, 0, sizeof(cbuf));
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mutex_lock(&ipclock);
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if (scu->dev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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for (nc = 0; nc < count; nc++, offset += 2) {
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cbuf[offset] = addr[nc];
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cbuf[offset + 1] = addr[nc] >> 8;
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}
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(scu, wbuf[nc], offset);
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ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
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ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
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}
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err = intel_scu_ipc_check_status(scu);
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if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(scu, nc);
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}
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mutex_unlock(&ipclock);
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return err;
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}
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/**
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* intel_scu_ipc_ioread8 - read a word via the SCU
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* @addr: register on SCU
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* @data: return pointer for read byte
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*
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* Read a single register. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread8(u16 addr, u8 *data)
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{
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return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread8);
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/**
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* intel_scu_ipc_ioread16 - read a word via the SCU
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* @addr: register on SCU
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* @data: return pointer for read word
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*
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* Read a register pair. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread16(u16 addr, u16 *data)
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{
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u16 x[2] = {addr, addr + 1};
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return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread16);
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/**
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* intel_scu_ipc_ioread32 - read a dword via the SCU
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* @addr: register on SCU
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* @data: return pointer for read dword
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*
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* Read four registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread32(u16 addr, u32 *data)
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{
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u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
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return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread32);
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/**
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* intel_scu_ipc_iowrite8 - write a byte via the SCU
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* @addr: register on SCU
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* @data: byte to write
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*
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* Write a single register. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite8(u16 addr, u8 data)
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{
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return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
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/**
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* intel_scu_ipc_iowrite16 - write a word via the SCU
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* @addr: register on SCU
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* @data: word to write
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*
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* Write two registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite16(u16 addr, u16 data)
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{
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u16 x[2] = {addr, addr + 1};
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return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
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/**
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* intel_scu_ipc_iowrite32 - write a dword via the SCU
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* @addr: register on SCU
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* @data: dword to write
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*
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* Write four registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite32(u16 addr, u32 data)
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{
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u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
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return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
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/**
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* intel_scu_ipc_readvv - read a set of registers
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* @addr: register list
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* @data: bytes to return
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* @len: length of array
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*
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* Read registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
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{
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return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_readv);
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/**
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* intel_scu_ipc_writev - write a set of registers
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* @addr: register list
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* @data: bytes to write
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* @len: length of array
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*
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* Write registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*
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*/
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int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
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{
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return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_writev);
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/**
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* intel_scu_ipc_update_register - r/m/w a register
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* @addr: register address
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* @bits: bits to update
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* @mask: mask of bits to update
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*
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* Read-modify-write power control unit register. The first data argument
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* must be register value and second is mask value
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* mask is a bitmap that indicates which bits to update.
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* 0 = masked. Don't modify this bit, 1 = modify this bit.
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* returns 0 on success or an error code.
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*
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* This function may sleep. Locking between SCU accesses is handled
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* for the caller.
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*/
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int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
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{
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u8 data[2] = { bits, mask };
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return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
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}
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EXPORT_SYMBOL(intel_scu_ipc_update_register);
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/**
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* intel_scu_ipc_simple_command - send a simple command
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* @cmd: command
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* @sub: sub type
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*
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* Issue a simple command to the SCU. Do not use this interface if
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* you must then access data as any data values may be overwritten
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* by another SCU access by the time this function returns.
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*
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* This function may sleep. Locking for SCU accesses is handled for
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* the caller.
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*/
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int intel_scu_ipc_simple_command(int cmd, int sub)
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{
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struct intel_scu_ipc_dev *scu = &ipcdev;
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int err;
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mutex_lock(&ipclock);
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if (scu->dev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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ipc_command(scu, sub << 12 | cmd);
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err = intel_scu_ipc_check_status(scu);
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mutex_unlock(&ipclock);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_simple_command);
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/**
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* intel_scu_ipc_command - command with data
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* @cmd: command
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* @sub: sub type
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* @in: input data
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* @inlen: input length in dwords
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* @out: output data
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|
* @outlein: output length in dwords
|
|
*
|
|
* Issue a command to the SCU which involves data transfers. Do the
|
|
* data copies under the lock but leave it for the caller to interpret
|
|
*/
|
|
int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
|
|
u32 *out, int outlen)
|
|
{
|
|
struct intel_scu_ipc_dev *scu = &ipcdev;
|
|
int i, err;
|
|
|
|
mutex_lock(&ipclock);
|
|
if (scu->dev == NULL) {
|
|
mutex_unlock(&ipclock);
|
|
return -ENODEV;
|
|
}
|
|
|
|
for (i = 0; i < inlen; i++)
|
|
ipc_data_writel(scu, *in++, 4 * i);
|
|
|
|
ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
|
|
err = intel_scu_ipc_check_status(scu);
|
|
|
|
if (!err) {
|
|
for (i = 0; i < outlen; i++)
|
|
*out++ = ipc_data_readl(scu, 4 * i);
|
|
}
|
|
|
|
mutex_unlock(&ipclock);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(intel_scu_ipc_command);
|
|
|
|
#define IPC_SPTR 0x08
|
|
#define IPC_DPTR 0x0C
|
|
|
|
/**
|
|
* intel_scu_ipc_raw_command() - IPC command with data and pointers
|
|
* @cmd: IPC command code.
|
|
* @sub: IPC command sub type.
|
|
* @in: input data of this IPC command.
|
|
* @inlen: input data length in dwords.
|
|
* @out: output data of this IPC command.
|
|
* @outlen: output data length in dwords.
|
|
* @sptr: data writing to SPTR register.
|
|
* @dptr: data writing to DPTR register.
|
|
*
|
|
* Send an IPC command to SCU with input/output data and source/dest pointers.
|
|
*
|
|
* Return: an IPC error code or 0 on success.
|
|
*/
|
|
int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
|
|
u32 *out, int outlen, u32 dptr, u32 sptr)
|
|
{
|
|
struct intel_scu_ipc_dev *scu = &ipcdev;
|
|
int inbuflen = DIV_ROUND_UP(inlen, 4);
|
|
u32 inbuf[4];
|
|
int i, err;
|
|
|
|
/* Up to 16 bytes */
|
|
if (inbuflen > 4)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&ipclock);
|
|
if (scu->dev == NULL) {
|
|
mutex_unlock(&ipclock);
|
|
return -ENODEV;
|
|
}
|
|
|
|
writel(dptr, scu->ipc_base + IPC_DPTR);
|
|
writel(sptr, scu->ipc_base + IPC_SPTR);
|
|
|
|
/*
|
|
* SRAM controller doesn't support 8-bit writes, it only
|
|
* supports 32-bit writes, so we have to copy input data into
|
|
* the temporary buffer, and SCU FW will use the inlen to
|
|
* determine the actual input data length in the temporary
|
|
* buffer.
|
|
*/
|
|
memcpy(inbuf, in, inlen);
|
|
|
|
for (i = 0; i < inbuflen; i++)
|
|
ipc_data_writel(scu, inbuf[i], 4 * i);
|
|
|
|
ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
|
|
err = intel_scu_ipc_check_status(scu);
|
|
if (!err) {
|
|
for (i = 0; i < outlen; i++)
|
|
*out++ = ipc_data_readl(scu, 4 * i);
|
|
}
|
|
|
|
mutex_unlock(&ipclock);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
|
|
|
|
/* I2C commands */
|
|
#define IPC_I2C_WRITE 1 /* I2C Write command */
|
|
#define IPC_I2C_READ 2 /* I2C Read command */
|
|
|
|
/**
|
|
* intel_scu_ipc_i2c_cntrl - I2C read/write operations
|
|
* @addr: I2C address + command bits
|
|
* @data: data to read/write
|
|
*
|
|
* Perform an an I2C read/write operation via the SCU. All locking is
|
|
* handled for the caller. This function may sleep.
|
|
*
|
|
* Returns an error code or 0 on success.
|
|
*
|
|
* This has to be in the IPC driver for the locking.
|
|
*/
|
|
int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
|
|
{
|
|
struct intel_scu_ipc_dev *scu = &ipcdev;
|
|
u32 cmd = 0;
|
|
|
|
mutex_lock(&ipclock);
|
|
if (scu->dev == NULL) {
|
|
mutex_unlock(&ipclock);
|
|
return -ENODEV;
|
|
}
|
|
cmd = (addr >> 24) & 0xFF;
|
|
if (cmd == IPC_I2C_READ) {
|
|
writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
|
|
/* Write not getting updated without delay */
|
|
mdelay(1);
|
|
*data = readl(scu->i2c_base + I2C_DATA_ADDR);
|
|
} else if (cmd == IPC_I2C_WRITE) {
|
|
writel(*data, scu->i2c_base + I2C_DATA_ADDR);
|
|
mdelay(1);
|
|
writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
|
|
} else {
|
|
dev_err(scu->dev,
|
|
"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
|
|
|
|
mutex_unlock(&ipclock);
|
|
return -EIO;
|
|
}
|
|
mutex_unlock(&ipclock);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
|
|
|
|
/*
|
|
* Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
|
|
* When ioc bit is set to 1, caller api must wait for interrupt handler called
|
|
* which in turn unlocks the caller api. Currently this is not used
|
|
*
|
|
* This is edge triggered so we need take no action to clear anything
|
|
*/
|
|
static irqreturn_t ioc(int irq, void *dev_id)
|
|
{
|
|
struct intel_scu_ipc_dev *scu = dev_id;
|
|
|
|
if (scu->irq_mode)
|
|
complete(&scu->cmd_complete);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* ipc_probe - probe an Intel SCU IPC
|
|
* @pdev: the PCI device matching
|
|
* @id: entry in the match table
|
|
*
|
|
* Enable and install an intel SCU IPC. This appears in the PCI space
|
|
* but uses some hard coded addresses as well.
|
|
*/
|
|
static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
int err;
|
|
struct intel_scu_ipc_dev *scu = &ipcdev;
|
|
struct intel_scu_ipc_pdata_t *pdata;
|
|
|
|
if (scu->dev) /* We support only one SCU */
|
|
return -EBUSY;
|
|
|
|
pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
|
|
if (!pdata)
|
|
return -ENODEV;
|
|
|
|
scu->irq_mode = pdata->irq_mode;
|
|
|
|
err = pcim_enable_device(pdev);
|
|
if (err)
|
|
return err;
|
|
|
|
err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
|
|
if (err)
|
|
return err;
|
|
|
|
init_completion(&scu->cmd_complete);
|
|
|
|
scu->ipc_base = pcim_iomap_table(pdev)[0];
|
|
|
|
scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
|
|
if (!scu->i2c_base)
|
|
return -ENOMEM;
|
|
|
|
err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
|
|
scu);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Assign device at last */
|
|
scu->dev = &pdev->dev;
|
|
|
|
intel_scu_devices_create();
|
|
|
|
pci_set_drvdata(pdev, scu);
|
|
return 0;
|
|
}
|
|
|
|
#define SCU_DEVICE(id, pdata) {PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
|
|
|
|
static const struct pci_device_id pci_ids[] = {
|
|
SCU_DEVICE(PCI_DEVICE_ID_LINCROFT, intel_scu_ipc_lincroft_pdata),
|
|
SCU_DEVICE(PCI_DEVICE_ID_PENWELL, intel_scu_ipc_penwell_pdata),
|
|
SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW, intel_scu_ipc_penwell_pdata),
|
|
SCU_DEVICE(PCI_DEVICE_ID_TANGIER, intel_scu_ipc_tangier_pdata),
|
|
{}
|
|
};
|
|
|
|
static struct pci_driver ipc_driver = {
|
|
.driver = {
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.name = "intel_scu_ipc",
|
|
.id_table = pci_ids,
|
|
.probe = ipc_probe,
|
|
};
|
|
builtin_pci_driver(ipc_driver);
|