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97417f6182
Flow entropy is calculated on the inner packet headers and used for flow distribution in processing, routing etc. For GRE-type encapsulations the entropy value is placed in the eight LSB of the key field in the GRE header as defined in NVGRE RFC 7637. For UDP based encapsulations the entropy value is placed in the source port of the UDP header. The hardware may support entropy calculation specifically for GRE and for all tunneling protocols. With commitdf2ef3bff1("net/mlx5e: Add GRE protocol offloading") GRE is offloaded, but the hardware is configured by default to calculate flow entropy so packets transmitted on the wire have a wrong key. To support UDP based tunnels (i.e VXLAN), GRE (i.e. no flow entropy) and NVGRE (i.e. with flow entropy) the hardware behaviour must be controlled by the driver. Ensure port entropy calculation is enabled for offloaded VXLAN tunnels and disable port entropy calculation in the presence of offloaded GRE tunnels by monitoring the presence of entropy enabling tunnels (i.e VXLAN) and entropy disabing tunnels (i.e GRE). Fixes:df2ef3bff1("net/mlx5e: Add GRE protocol offloading") Signed-off-by: Eli Britstein <elibr@mellanox.com> Reviewed-by: Oz Shlomo <ozsh@mellanox.com> Reviewed-by: Roi Dayan <roid@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
201 lines
7.0 KiB
C
201 lines
7.0 KiB
C
/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_PORT_H__
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#define __MLX5_PORT_H__
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#include <linux/mlx5/driver.h>
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enum mlx5_beacon_duration {
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MLX5_BEACON_DURATION_OFF = 0x0,
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MLX5_BEACON_DURATION_INF = 0xffff,
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};
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enum mlx5_module_id {
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MLX5_MODULE_ID_SFP = 0x3,
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MLX5_MODULE_ID_QSFP = 0xC,
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MLX5_MODULE_ID_QSFP_PLUS = 0xD,
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MLX5_MODULE_ID_QSFP28 = 0x11,
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};
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enum mlx5_an_status {
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MLX5_AN_UNAVAILABLE = 0,
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MLX5_AN_COMPLETE = 1,
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MLX5_AN_FAILED = 2,
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MLX5_AN_LINK_UP = 3,
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MLX5_AN_LINK_DOWN = 4,
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};
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#define MLX5_EEPROM_MAX_BYTES 32
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#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
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#define MLX5_I2C_ADDR_LOW 0x50
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#define MLX5_I2C_ADDR_HIGH 0x51
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#define MLX5_EEPROM_PAGE_LENGTH 256
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enum mlx5e_link_mode {
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MLX5E_1000BASE_CX_SGMII = 0,
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MLX5E_1000BASE_KX = 1,
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MLX5E_10GBASE_CX4 = 2,
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MLX5E_10GBASE_KX4 = 3,
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MLX5E_10GBASE_KR = 4,
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MLX5E_20GBASE_KR2 = 5,
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MLX5E_40GBASE_CR4 = 6,
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MLX5E_40GBASE_KR4 = 7,
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MLX5E_56GBASE_R4 = 8,
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MLX5E_10GBASE_CR = 12,
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MLX5E_10GBASE_SR = 13,
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MLX5E_10GBASE_ER = 14,
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MLX5E_40GBASE_SR4 = 15,
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MLX5E_40GBASE_LR4 = 16,
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MLX5E_50GBASE_SR2 = 18,
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MLX5E_100GBASE_CR4 = 20,
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MLX5E_100GBASE_SR4 = 21,
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MLX5E_100GBASE_KR4 = 22,
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MLX5E_100GBASE_LR4 = 23,
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MLX5E_100BASE_TX = 24,
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MLX5E_1000BASE_T = 25,
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MLX5E_10GBASE_T = 26,
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MLX5E_25GBASE_CR = 27,
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MLX5E_25GBASE_KR = 28,
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MLX5E_25GBASE_SR = 29,
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MLX5E_50GBASE_CR2 = 30,
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MLX5E_50GBASE_KR2 = 31,
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MLX5E_LINK_MODES_NUMBER,
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};
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enum mlx5e_ext_link_mode {
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MLX5E_SGMII_100M = 0,
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MLX5E_1000BASE_X_SGMII = 1,
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MLX5E_5GBASE_R = 3,
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MLX5E_10GBASE_XFI_XAUI_1 = 4,
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MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
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MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
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MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
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MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
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MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
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MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
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MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
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MLX5E_400GAUI_8 = 15,
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MLX5E_EXT_LINK_MODES_NUMBER,
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};
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enum mlx5e_connector_type {
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MLX5E_PORT_UNKNOWN = 0,
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MLX5E_PORT_NONE = 1,
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MLX5E_PORT_TP = 2,
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MLX5E_PORT_AUI = 3,
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MLX5E_PORT_BNC = 4,
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MLX5E_PORT_MII = 5,
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MLX5E_PORT_FIBRE = 6,
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MLX5E_PORT_DA = 7,
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MLX5E_PORT_OTHER = 8,
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MLX5E_CONNECTOR_TYPE_NUMBER,
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};
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#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
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#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
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(ext ? MLX5_GET(reg, out, ext_##field) : \
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MLX5_GET(reg, out, field))
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int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
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int ptys_size, int proto_mask, u8 local_port);
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int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
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u8 *link_width_oper, u8 local_port);
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int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
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u8 *proto_oper, u8 local_port);
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void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
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int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status status);
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int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status *status);
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int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
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int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
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void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
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void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
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u8 port);
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int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
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u8 *vl_hw_cap, u8 local_port);
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int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
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int mlx5_query_port_pause(struct mlx5_core_dev *dev,
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u32 *rx_pause, u32 *tx_pause);
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int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
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int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
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u8 *pfc_en_rx);
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int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
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u16 stall_critical_watermark,
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u16 stall_minor_watermark);
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int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
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u16 *stall_critical_watermark, u16 *stall_minor_watermark);
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int mlx5_max_tc(struct mlx5_core_dev *mdev);
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int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
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int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
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u8 prio, u8 *tc);
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int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
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int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
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u8 tc, u8 *tc_group);
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int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
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int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
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u8 tc, u8 *bw_pct);
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int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
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u8 *max_bw_value,
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u8 *max_bw_unit);
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int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
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u8 *max_bw_value,
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u8 *max_bw_unit);
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int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
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int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
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int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
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int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
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int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
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void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
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bool *enabled);
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int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
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u16 offset, u16 size, u8 *data);
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int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
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int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
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int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
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int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
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int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
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int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
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#endif /* __MLX5_PORT_H__ */
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