mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 00:42:08 +07:00
96ebb30732
Currently, the debugfs control node can't parse bash-like commands. Now add such support for any tester that uses scripts. v2: squash in fixes for input validation Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1439 lines
32 KiB
C
1439 lines
32 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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struct ras_ih_data {
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/* interrupt bottom half */
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struct work_struct ih_work;
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int inuse;
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/* IP callback */
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ras_ih_cb cb;
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/* full of entries */
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unsigned char *ring;
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unsigned int ring_size;
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unsigned int element_size;
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unsigned int aligned_element_size;
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unsigned int rptr;
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unsigned int wptr;
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};
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struct ras_fs_data {
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char sysfs_name[32];
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char debugfs_name[32];
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};
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struct ras_err_data {
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unsigned long ue_count;
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unsigned long ce_count;
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};
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struct ras_err_handler_data {
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/* point to bad pages array */
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struct {
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unsigned long bp;
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struct amdgpu_bo *bo;
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} *bps;
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/* the count of entries */
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int count;
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/* the space can place new entries */
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int space_left;
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/* last reserved entry's index + 1 */
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int last_reserved;
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};
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struct ras_manager {
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struct ras_common_if head;
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/* reference count */
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int use;
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/* ras block link */
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struct list_head node;
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/* the device */
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struct amdgpu_device *adev;
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/* debugfs */
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struct dentry *ent;
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/* sysfs */
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struct device_attribute sysfs_attr;
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int attr_inuse;
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/* fs node name */
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struct ras_fs_data fs_data;
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/* IH data */
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struct ras_ih_data ih_data;
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struct ras_err_data err_data;
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};
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const char *ras_error_string[] = {
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"none",
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"parity",
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"single_correctable",
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"multi_uncorrectable",
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"poison",
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};
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const char *ras_block_string[] = {
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"umc",
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"sdma",
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"gfx",
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"mmhub",
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"athub",
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"pcie_bif",
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"hdp",
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"xgmi_wafl",
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"df",
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"smn",
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"sem",
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"mp0",
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"mp1",
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"fuse",
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};
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#define ras_err_str(i) (ras_error_string[ffs(i)])
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#define ras_block_str(i) (ras_block_string[i])
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static void amdgpu_ras_self_test(struct amdgpu_device *adev)
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{
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/* TODO */
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}
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static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
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struct ras_query_if info = {
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.head = obj->head,
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};
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ssize_t s;
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char val[128];
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if (amdgpu_ras_error_query(obj->adev, &info))
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return -EINVAL;
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s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
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"ue", info.ue_count,
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"ce", info.ce_count);
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if (*pos >= s)
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return 0;
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s -= *pos;
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s = min_t(u64, s, size);
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if (copy_to_user(buf, &val[*pos], s))
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return -EINVAL;
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*pos += s;
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return s;
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}
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static ssize_t amdgpu_ras_debugfs_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
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struct ras_inject_if info = {
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.head = obj->head,
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};
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ssize_t s = min_t(u64, 64, size);
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char val[64];
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char *str = val;
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memset(val, 0, sizeof(val));
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if (*pos)
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return -EINVAL;
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if (copy_from_user(str, buf, s))
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return -EINVAL;
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/* only care ue/ce for now. */
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if (memcmp(str, "ue", 2) == 0) {
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info.head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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str += 2;
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} else if (memcmp(str, "ce", 2) == 0) {
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info.head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
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str += 2;
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}
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if (sscanf(str, "0x%llx 0x%llx", &info.address, &info.value) != 2) {
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if (sscanf(str, "%llu %llu", &info.address, &info.value) != 2)
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return -EINVAL;
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}
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*pos = s;
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if (amdgpu_ras_error_inject(obj->adev, &info))
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return -EINVAL;
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return size;
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}
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static const struct file_operations amdgpu_ras_debugfs_ops = {
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.owner = THIS_MODULE,
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.read = amdgpu_ras_debugfs_read,
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.write = amdgpu_ras_debugfs_write,
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.llseek = default_llseek
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};
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static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
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*block_id = i;
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if (strcmp(name, ras_block_str(i)) == 0)
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return 0;
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}
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return -EINVAL;
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}
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static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
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const char __user *buf, size_t size,
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loff_t *pos, struct ras_debug_if *data)
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{
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ssize_t s = min_t(u64, 64, size);
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char str[65];
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char block_name[33];
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char err[9] = "ue";
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int op = -1;
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int block_id;
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u64 address, value;
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if (*pos)
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return -EINVAL;
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*pos = size;
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memset(str, 0, sizeof(str));
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memset(data, 0, sizeof(*data));
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if (copy_from_user(str, buf, s))
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return -EINVAL;
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if (sscanf(str, "disable %32s", block_name) == 1)
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op = 0;
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else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
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op = 1;
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else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
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op = 2;
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else if (sscanf(str, "%32s", block_name) == 1)
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/* ascii string, but commands are not matched. */
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return -EINVAL;
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if (op != -1) {
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if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
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return -EINVAL;
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data->head.block = block_id;
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data->head.type = memcmp("ue", err, 2) == 0 ?
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AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
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data->op = op;
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if (op == 2) {
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if (sscanf(str, "%*s %*s %*s %llu %llu",
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&address, &value) != 2)
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if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx",
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&address, &value) != 2)
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return -EINVAL;
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data->inject.address = address;
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data->inject.value = value;
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}
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} else {
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if (size < sizeof(data))
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return -EINVAL;
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if (copy_from_user(data, buf, sizeof(*data)))
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return -EINVAL;
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}
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return 0;
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}
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/*
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* DOC: ras debugfs control interface
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*
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* It accepts struct ras_debug_if who has two members.
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*
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* First member: ras_debug_if::head or ras_debug_if::inject.
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*
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* head is used to indicate which IP block will be under control.
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*
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* head has four members, they are block, type, sub_block_index, name.
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* block: which IP will be under control.
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* type: what kind of error will be enabled/disabled/injected.
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* sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
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* name: the name of IP.
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*
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* inject has two more members than head, they are address, value.
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* As their names indicate, inject operation will write the
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* value to the address.
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*
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* Second member: struct ras_debug_if::op.
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* It has three kinds of operations.
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* 0: disable RAS on the block. Take ::head as its data.
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* 1: enable RAS on the block. Take ::head as its data.
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* 2: inject errors on the block. Take ::inject as its data.
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*
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* How to use the interface?
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* programs:
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* copy the struct ras_debug_if in your codes and initialize it.
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* write the struct to the control node.
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*
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* bash:
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* echo op block [error [address value]] > .../ras/ras_ctrl
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* op: disable, enable, inject
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* disable: only block is needed
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* enable: block and error are needed
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* inject: error, address, value are needed
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* block: umc, smda, gfx, .........
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* see ras_block_string[] for details
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* error: ue, ce
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* ue: multi_uncorrectable
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* ce: single_correctable
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*
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* here are some examples for bash commands,
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* echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
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* echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
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* echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
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*
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* How to check the result?
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*
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* For disable/enable, please check ras features at
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* /sys/class/drm/card[0/1/2...]/device/ras/features
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*
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* For inject, please check corresponding err count at
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* /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
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*
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* NOTE: operation is only allowed on blocks which are supported.
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* Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
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*/
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static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
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struct ras_debug_if data;
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int ret = 0;
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ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
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if (ret)
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return -EINVAL;
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if (!amdgpu_ras_is_supported(adev, data.head.block))
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return -EINVAL;
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switch (data.op) {
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case 0:
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ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
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break;
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case 1:
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ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
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break;
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case 2:
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ret = amdgpu_ras_error_inject(adev, &data.inject);
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break;
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default:
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ret = -EINVAL;
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break;
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};
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if (ret)
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return -EINVAL;
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return size;
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}
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static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
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.owner = THIS_MODULE,
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.read = NULL,
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.write = amdgpu_ras_debugfs_ctrl_write,
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.llseek = default_llseek
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};
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static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
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struct ras_query_if info = {
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.head = obj->head,
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};
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if (amdgpu_ras_error_query(obj->adev, &info))
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return -EINVAL;
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return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
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"ue", info.ue_count,
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"ce", info.ce_count);
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}
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/* obj begin */
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#define get_obj(obj) do { (obj)->use++; } while (0)
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#define alive_obj(obj) ((obj)->use)
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static inline void put_obj(struct ras_manager *obj)
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{
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if (obj && --obj->use == 0)
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list_del(&obj->node);
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if (obj && obj->use < 0) {
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DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
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}
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}
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/* make one obj and return it. */
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static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
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struct ras_common_if *head)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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if (!con)
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return NULL;
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if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
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return NULL;
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obj = &con->objs[head->block];
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/* already exist. return obj? */
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if (alive_obj(obj))
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return NULL;
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obj->head = *head;
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obj->adev = adev;
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list_add(&obj->node, &con->head);
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get_obj(obj);
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return obj;
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}
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/* return an obj equal to head, or the first when head is NULL */
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static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
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struct ras_common_if *head)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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int i;
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if (!con)
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return NULL;
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if (head) {
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if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
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return NULL;
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obj = &con->objs[head->block];
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if (alive_obj(obj)) {
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WARN_ON(head->block != obj->head.block);
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return obj;
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}
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} else {
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for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
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obj = &con->objs[i];
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if (alive_obj(obj)) {
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WARN_ON(i != obj->head.block);
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return obj;
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}
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}
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}
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return NULL;
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}
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/* obj end */
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/* feature ctl begin */
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static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
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struct ras_common_if *head)
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{
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return amdgpu_ras_enable && (amdgpu_ras_mask & BIT(head->block));
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}
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static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
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struct ras_common_if *head)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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return con->features & BIT(head->block);
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}
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/*
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* if obj is not created, then create one.
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* set feature enable flag.
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*/
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static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
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struct ras_common_if *head, int enable)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
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if (!amdgpu_ras_is_feature_allowed(adev, head))
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return 0;
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if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
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return 0;
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if (enable) {
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if (!obj) {
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obj = amdgpu_ras_create_obj(adev, head);
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if (!obj)
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return -EINVAL;
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} else {
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/* In case we create obj somewhere else */
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get_obj(obj);
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}
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con->features |= BIT(head->block);
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} else {
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if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
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con->features &= ~BIT(head->block);
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put_obj(obj);
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}
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}
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return 0;
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}
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/* wrapper of psp_ras_enable_features */
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int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
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struct ras_common_if *head, bool enable)
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{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
union ta_ras_cmd_input info;
|
|
int ret;
|
|
|
|
if (!con)
|
|
return -EINVAL;
|
|
|
|
if (!enable) {
|
|
info.disable_features = (struct ta_ras_disable_features_input) {
|
|
.block_id = head->block,
|
|
.error_type = head->type,
|
|
};
|
|
} else {
|
|
info.enable_features = (struct ta_ras_enable_features_input) {
|
|
.block_id = head->block,
|
|
.error_type = head->type,
|
|
};
|
|
}
|
|
|
|
/* Do not enable if it is not allowed. */
|
|
WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
|
|
/* Are we alerady in that state we are going to set? */
|
|
if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
|
|
return 0;
|
|
|
|
ret = psp_ras_enable_features(&adev->psp, &info, enable);
|
|
if (ret) {
|
|
DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
|
|
enable ? "enable":"disable",
|
|
ras_block_str(head->block),
|
|
ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* setup the obj */
|
|
__amdgpu_ras_feature_enable(adev, head, enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
|
|
bool bypass)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj, *tmp;
|
|
|
|
list_for_each_entry_safe(obj, tmp, &con->head, node) {
|
|
/* bypass psp.
|
|
* aka just release the obj and corresponding flags
|
|
*/
|
|
if (bypass) {
|
|
if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
|
|
break;
|
|
} else {
|
|
if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
|
|
break;
|
|
}
|
|
};
|
|
|
|
return con->features;
|
|
}
|
|
|
|
static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
|
|
bool bypass)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
|
|
int i;
|
|
|
|
for (i = 0; i < ras_block_count; i++) {
|
|
struct ras_common_if head = {
|
|
.block = i,
|
|
.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
|
|
.sub_block_index = 0,
|
|
};
|
|
strcpy(head.name, ras_block_str(i));
|
|
if (bypass) {
|
|
/*
|
|
* bypass psp. vbios enable ras for us.
|
|
* so just create the obj
|
|
*/
|
|
if (__amdgpu_ras_feature_enable(adev, &head, 1))
|
|
break;
|
|
} else {
|
|
if (amdgpu_ras_feature_enable(adev, &head, 1))
|
|
break;
|
|
}
|
|
};
|
|
|
|
return con->features;
|
|
}
|
|
/* feature ctl end */
|
|
|
|
/* query/inject/cure begin */
|
|
int amdgpu_ras_error_query(struct amdgpu_device *adev,
|
|
struct ras_query_if *info)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
|
|
|
if (!obj)
|
|
return -EINVAL;
|
|
/* TODO might read the register to read the count */
|
|
|
|
info->ue_count = obj->err_data.ue_count;
|
|
info->ce_count = obj->err_data.ce_count;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* wrapper of psp_ras_trigger_error */
|
|
int amdgpu_ras_error_inject(struct amdgpu_device *adev,
|
|
struct ras_inject_if *info)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
|
struct ta_ras_trigger_error_input block_info = {
|
|
.block_id = info->head.block,
|
|
.inject_error_type = info->head.type,
|
|
.sub_block_index = info->head.sub_block_index,
|
|
.address = info->address,
|
|
.value = info->value,
|
|
};
|
|
int ret = 0;
|
|
|
|
if (!obj)
|
|
return -EINVAL;
|
|
|
|
ret = psp_ras_trigger_error(&adev->psp, &block_info);
|
|
if (ret)
|
|
DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
|
|
ras_block_str(info->head.block),
|
|
ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int amdgpu_ras_error_cure(struct amdgpu_device *adev,
|
|
struct ras_cure_if *info)
|
|
{
|
|
/* psp fw has no cure interface for now. */
|
|
return 0;
|
|
}
|
|
|
|
/* get the total error counts on all IPs */
|
|
int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
|
|
bool is_ce)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj;
|
|
struct ras_err_data data = {0, 0};
|
|
|
|
if (!con)
|
|
return -EINVAL;
|
|
|
|
list_for_each_entry(obj, &con->head, node) {
|
|
struct ras_query_if info = {
|
|
.head = obj->head,
|
|
};
|
|
|
|
if (amdgpu_ras_error_query(adev, &info))
|
|
return -EINVAL;
|
|
|
|
data.ce_count += info.ce_count;
|
|
data.ue_count += info.ue_count;
|
|
}
|
|
|
|
return is_ce ? data.ce_count : data.ue_count;
|
|
}
|
|
/* query/inject/cure end */
|
|
|
|
|
|
/* sysfs begin */
|
|
|
|
static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct amdgpu_ras *con =
|
|
container_of(attr, struct amdgpu_ras, features_attr);
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct amdgpu_device *adev = ddev->dev_private;
|
|
struct ras_common_if head;
|
|
int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
|
|
int i;
|
|
ssize_t s;
|
|
struct ras_manager *obj;
|
|
|
|
s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
|
|
|
|
for (i = 0; i < ras_block_count; i++) {
|
|
head.block = i;
|
|
|
|
if (amdgpu_ras_is_feature_enabled(adev, &head)) {
|
|
obj = amdgpu_ras_find_obj(adev, &head);
|
|
s += scnprintf(&buf[s], PAGE_SIZE - s,
|
|
"%s: %s\n",
|
|
ras_block_str(i),
|
|
ras_err_str(obj->head.type));
|
|
} else
|
|
s += scnprintf(&buf[s], PAGE_SIZE - s,
|
|
"%s: disabled\n",
|
|
ras_block_str(i));
|
|
}
|
|
|
|
return s;
|
|
}
|
|
|
|
static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct attribute *attrs[] = {
|
|
&con->features_attr.attr,
|
|
NULL
|
|
};
|
|
struct attribute_group group = {
|
|
.name = "ras",
|
|
.attrs = attrs,
|
|
};
|
|
|
|
con->features_attr = (struct device_attribute) {
|
|
.attr = {
|
|
.name = "features",
|
|
.mode = S_IRUGO,
|
|
},
|
|
.show = amdgpu_ras_sysfs_features_read,
|
|
};
|
|
|
|
return sysfs_create_group(&adev->dev->kobj, &group);
|
|
}
|
|
|
|
static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct attribute *attrs[] = {
|
|
&con->features_attr.attr,
|
|
NULL
|
|
};
|
|
struct attribute_group group = {
|
|
.name = "ras",
|
|
.attrs = attrs,
|
|
};
|
|
|
|
sysfs_remove_group(&adev->dev->kobj, &group);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
|
|
struct ras_fs_if *head)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
|
|
|
|
if (!obj || obj->attr_inuse)
|
|
return -EINVAL;
|
|
|
|
get_obj(obj);
|
|
|
|
memcpy(obj->fs_data.sysfs_name,
|
|
head->sysfs_name,
|
|
sizeof(obj->fs_data.sysfs_name));
|
|
|
|
obj->sysfs_attr = (struct device_attribute){
|
|
.attr = {
|
|
.name = obj->fs_data.sysfs_name,
|
|
.mode = S_IRUGO,
|
|
},
|
|
.show = amdgpu_ras_sysfs_read,
|
|
};
|
|
|
|
if (sysfs_add_file_to_group(&adev->dev->kobj,
|
|
&obj->sysfs_attr.attr,
|
|
"ras")) {
|
|
put_obj(obj);
|
|
return -EINVAL;
|
|
}
|
|
|
|
obj->attr_inuse = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
|
|
struct ras_common_if *head)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
|
|
|
|
if (!obj || !obj->attr_inuse)
|
|
return -EINVAL;
|
|
|
|
sysfs_remove_file_from_group(&adev->dev->kobj,
|
|
&obj->sysfs_attr.attr,
|
|
"ras");
|
|
obj->attr_inuse = 0;
|
|
put_obj(obj);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj, *tmp;
|
|
|
|
list_for_each_entry_safe(obj, tmp, &con->head, node) {
|
|
amdgpu_ras_sysfs_remove(adev, &obj->head);
|
|
}
|
|
|
|
amdgpu_ras_sysfs_remove_feature_node(adev);
|
|
|
|
return 0;
|
|
}
|
|
/* sysfs end */
|
|
|
|
/* debugfs begin */
|
|
static int amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct drm_minor *minor = adev->ddev->primary;
|
|
struct dentry *root = minor->debugfs_root, *dir;
|
|
struct dentry *ent;
|
|
|
|
dir = debugfs_create_dir("ras", root);
|
|
if (IS_ERR(dir))
|
|
return -EINVAL;
|
|
|
|
con->dir = dir;
|
|
|
|
ent = debugfs_create_file("ras_ctrl",
|
|
S_IWUGO | S_IRUGO, con->dir,
|
|
adev, &amdgpu_ras_debugfs_ctrl_ops);
|
|
if (IS_ERR(ent)) {
|
|
debugfs_remove(con->dir);
|
|
return -EINVAL;
|
|
}
|
|
|
|
con->ent = ent;
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
|
|
struct ras_fs_if *head)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
|
|
struct dentry *ent;
|
|
|
|
if (!obj || obj->ent)
|
|
return -EINVAL;
|
|
|
|
get_obj(obj);
|
|
|
|
memcpy(obj->fs_data.debugfs_name,
|
|
head->debugfs_name,
|
|
sizeof(obj->fs_data.debugfs_name));
|
|
|
|
ent = debugfs_create_file(obj->fs_data.debugfs_name,
|
|
S_IWUGO | S_IRUGO, con->dir,
|
|
obj, &amdgpu_ras_debugfs_ops);
|
|
|
|
if (IS_ERR(ent))
|
|
return -EINVAL;
|
|
|
|
obj->ent = ent;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
|
|
struct ras_common_if *head)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
|
|
|
|
if (!obj || !obj->ent)
|
|
return 0;
|
|
|
|
debugfs_remove(obj->ent);
|
|
obj->ent = NULL;
|
|
put_obj(obj);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj, *tmp;
|
|
|
|
list_for_each_entry_safe(obj, tmp, &con->head, node) {
|
|
amdgpu_ras_debugfs_remove(adev, &obj->head);
|
|
}
|
|
|
|
debugfs_remove(con->ent);
|
|
debugfs_remove(con->dir);
|
|
con->dir = NULL;
|
|
con->ent = NULL;
|
|
|
|
return 0;
|
|
}
|
|
/* debugfs end */
|
|
|
|
/* ras fs */
|
|
|
|
static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_ras_sysfs_create_feature_node(adev);
|
|
amdgpu_ras_debugfs_create_ctrl_node(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_ras_debugfs_remove_all(adev);
|
|
amdgpu_ras_sysfs_remove_all(adev);
|
|
return 0;
|
|
}
|
|
/* ras fs end */
|
|
|
|
/* ih begin */
|
|
static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
|
|
{
|
|
struct ras_ih_data *data = &obj->ih_data;
|
|
struct amdgpu_iv_entry entry;
|
|
int ret;
|
|
|
|
while (data->rptr != data->wptr) {
|
|
rmb();
|
|
memcpy(&entry, &data->ring[data->rptr],
|
|
data->element_size);
|
|
|
|
wmb();
|
|
data->rptr = (data->aligned_element_size +
|
|
data->rptr) % data->ring_size;
|
|
|
|
/* Let IP handle its data, maybe we need get the output
|
|
* from the callback to udpate the error type/count, etc
|
|
*/
|
|
if (data->cb) {
|
|
ret = data->cb(obj->adev, &entry);
|
|
/* ue will trigger an interrupt, and in that case
|
|
* we need do a reset to recovery the whole system.
|
|
* But leave IP do that recovery, here we just dispatch
|
|
* the error.
|
|
*/
|
|
if (ret == AMDGPU_RAS_UE) {
|
|
obj->err_data.ue_count++;
|
|
}
|
|
/* Might need get ce count by register, but not all IP
|
|
* saves ce count, some IP just use one bit or two bits
|
|
* to indicate ce happened.
|
|
*/
|
|
}
|
|
}
|
|
}
|
|
|
|
static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
|
|
{
|
|
struct ras_ih_data *data =
|
|
container_of(work, struct ras_ih_data, ih_work);
|
|
struct ras_manager *obj =
|
|
container_of(data, struct ras_manager, ih_data);
|
|
|
|
amdgpu_ras_interrupt_handler(obj);
|
|
}
|
|
|
|
int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
|
|
struct ras_dispatch_if *info)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
|
struct ras_ih_data *data = &obj->ih_data;
|
|
|
|
if (!obj)
|
|
return -EINVAL;
|
|
|
|
if (data->inuse == 0)
|
|
return 0;
|
|
|
|
/* Might be overflow... */
|
|
memcpy(&data->ring[data->wptr], info->entry,
|
|
data->element_size);
|
|
|
|
wmb();
|
|
data->wptr = (data->aligned_element_size +
|
|
data->wptr) % data->ring_size;
|
|
|
|
schedule_work(&data->ih_work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
|
|
struct ras_ih_if *info)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
|
struct ras_ih_data *data;
|
|
|
|
if (!obj)
|
|
return -EINVAL;
|
|
|
|
data = &obj->ih_data;
|
|
if (data->inuse == 0)
|
|
return 0;
|
|
|
|
cancel_work_sync(&data->ih_work);
|
|
|
|
kfree(data->ring);
|
|
memset(data, 0, sizeof(*data));
|
|
put_obj(obj);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
|
|
struct ras_ih_if *info)
|
|
{
|
|
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
|
struct ras_ih_data *data;
|
|
|
|
if (!obj) {
|
|
/* in case we registe the IH before enable ras feature */
|
|
obj = amdgpu_ras_create_obj(adev, &info->head);
|
|
if (!obj)
|
|
return -EINVAL;
|
|
} else
|
|
get_obj(obj);
|
|
|
|
data = &obj->ih_data;
|
|
/* add the callback.etc */
|
|
*data = (struct ras_ih_data) {
|
|
.inuse = 0,
|
|
.cb = info->cb,
|
|
.element_size = sizeof(struct amdgpu_iv_entry),
|
|
.rptr = 0,
|
|
.wptr = 0,
|
|
};
|
|
|
|
INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
|
|
|
|
data->aligned_element_size = ALIGN(data->element_size, 8);
|
|
/* the ring can store 64 iv entries. */
|
|
data->ring_size = 64 * data->aligned_element_size;
|
|
data->ring = kmalloc(data->ring_size, GFP_KERNEL);
|
|
if (!data->ring) {
|
|
put_obj(obj);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* IH is ready */
|
|
data->inuse = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_manager *obj, *tmp;
|
|
|
|
list_for_each_entry_safe(obj, tmp, &con->head, node) {
|
|
struct ras_ih_if info = {
|
|
.head = obj->head,
|
|
};
|
|
amdgpu_ras_interrupt_remove_handler(adev, &info);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
/* ih end */
|
|
|
|
/* recovery begin */
|
|
static void amdgpu_ras_do_recovery(struct work_struct *work)
|
|
{
|
|
struct amdgpu_ras *ras =
|
|
container_of(work, struct amdgpu_ras, recovery_work);
|
|
|
|
amdgpu_device_gpu_recover(ras->adev, 0);
|
|
atomic_set(&ras->in_recovery, 0);
|
|
}
|
|
|
|
static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
|
|
struct amdgpu_bo **bo_ptr)
|
|
{
|
|
/* no need to free it actually. */
|
|
amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
|
|
return 0;
|
|
}
|
|
|
|
/* reserve vram with size@offset */
|
|
static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
|
|
uint64_t offset, uint64_t size,
|
|
struct amdgpu_bo **bo_ptr)
|
|
{
|
|
struct ttm_operation_ctx ctx = { false, false };
|
|
struct amdgpu_bo_param bp;
|
|
int r = 0;
|
|
int i;
|
|
struct amdgpu_bo *bo;
|
|
|
|
if (bo_ptr)
|
|
*bo_ptr = NULL;
|
|
memset(&bp, 0, sizeof(bp));
|
|
bp.size = size;
|
|
bp.byte_align = PAGE_SIZE;
|
|
bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
|
|
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
|
|
AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
|
|
bp.type = ttm_bo_type_kernel;
|
|
bp.resv = NULL;
|
|
|
|
r = amdgpu_bo_create(adev, &bp, &bo);
|
|
if (r)
|
|
return -EINVAL;
|
|
|
|
r = amdgpu_bo_reserve(bo, false);
|
|
if (r)
|
|
goto error_reserve;
|
|
|
|
offset = ALIGN(offset, PAGE_SIZE);
|
|
for (i = 0; i < bo->placement.num_placement; ++i) {
|
|
bo->placements[i].fpfn = offset >> PAGE_SHIFT;
|
|
bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
|
|
}
|
|
|
|
ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
|
|
r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
|
|
if (r)
|
|
goto error_pin;
|
|
|
|
r = amdgpu_bo_pin_restricted(bo,
|
|
AMDGPU_GEM_DOMAIN_VRAM,
|
|
offset,
|
|
offset + size);
|
|
if (r)
|
|
goto error_pin;
|
|
|
|
if (bo_ptr)
|
|
*bo_ptr = bo;
|
|
|
|
amdgpu_bo_unreserve(bo);
|
|
return r;
|
|
|
|
error_pin:
|
|
amdgpu_bo_unreserve(bo);
|
|
error_reserve:
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
/* alloc/realloc bps array */
|
|
static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
|
|
struct ras_err_handler_data *data, int pages)
|
|
{
|
|
unsigned int old_space = data->count + data->space_left;
|
|
unsigned int new_space = old_space + pages;
|
|
unsigned int align_space = ALIGN(new_space, 1024);
|
|
void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
|
|
|
|
if (!tmp)
|
|
return -ENOMEM;
|
|
|
|
if (data->bps) {
|
|
memcpy(tmp, data->bps,
|
|
data->count * sizeof(*data->bps));
|
|
kfree(data->bps);
|
|
}
|
|
|
|
data->bps = tmp;
|
|
data->space_left += align_space - old_space;
|
|
return 0;
|
|
}
|
|
|
|
/* it deal with vram only. */
|
|
int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
|
|
unsigned long *bps, int pages)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_err_handler_data *data = con->eh_data;
|
|
int i = pages;
|
|
int ret = 0;
|
|
|
|
if (!con || !data || !bps || pages <= 0)
|
|
return 0;
|
|
|
|
mutex_lock(&con->recovery_lock);
|
|
if (!data)
|
|
goto out;
|
|
|
|
if (data->space_left <= pages)
|
|
if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
while (i--)
|
|
data->bps[data->count++].bp = bps[i];
|
|
|
|
data->space_left -= pages;
|
|
out:
|
|
mutex_unlock(&con->recovery_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* called in gpu recovery/init */
|
|
int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_err_handler_data *data = con->eh_data;
|
|
uint64_t bp;
|
|
struct amdgpu_bo *bo;
|
|
int i;
|
|
|
|
if (!con || !data)
|
|
return 0;
|
|
|
|
mutex_lock(&con->recovery_lock);
|
|
/* reserve vram at driver post stage. */
|
|
for (i = data->last_reserved; i < data->count; i++) {
|
|
bp = data->bps[i].bp;
|
|
|
|
if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
|
|
PAGE_SIZE, &bo))
|
|
DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
|
|
|
|
data->bps[i].bo = bo;
|
|
data->last_reserved = i + 1;
|
|
}
|
|
mutex_unlock(&con->recovery_lock);
|
|
return 0;
|
|
}
|
|
|
|
/* called when driver unload */
|
|
static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_err_handler_data *data = con->eh_data;
|
|
struct amdgpu_bo *bo;
|
|
int i;
|
|
|
|
if (!con || !data)
|
|
return 0;
|
|
|
|
mutex_lock(&con->recovery_lock);
|
|
for (i = data->last_reserved - 1; i >= 0; i--) {
|
|
bo = data->bps[i].bo;
|
|
|
|
amdgpu_ras_release_vram(adev, &bo);
|
|
|
|
data->bps[i].bo = bo;
|
|
data->last_reserved = i;
|
|
}
|
|
mutex_unlock(&con->recovery_lock);
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
|
|
{
|
|
/* TODO
|
|
* write the array to eeprom when SMU disabled.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
|
|
{
|
|
/* TODO
|
|
* read the array to eeprom when SMU disabled.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_err_handler_data **data = &con->eh_data;
|
|
|
|
*data = kmalloc(sizeof(**data),
|
|
GFP_KERNEL|__GFP_ZERO);
|
|
if (!*data)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&con->recovery_lock);
|
|
INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
|
|
atomic_set(&con->in_recovery, 0);
|
|
con->adev = adev;
|
|
|
|
amdgpu_ras_load_bad_pages(adev);
|
|
amdgpu_ras_reserve_bad_pages(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
struct ras_err_handler_data *data = con->eh_data;
|
|
|
|
cancel_work_sync(&con->recovery_work);
|
|
amdgpu_ras_save_bad_pages(adev);
|
|
amdgpu_ras_release_bad_pages(adev);
|
|
|
|
mutex_lock(&con->recovery_lock);
|
|
con->eh_data = NULL;
|
|
kfree(data->bps);
|
|
kfree(data);
|
|
mutex_unlock(&con->recovery_lock);
|
|
|
|
return 0;
|
|
}
|
|
/* recovery end */
|
|
|
|
struct ras_DID_capability {
|
|
u16 did;
|
|
u8 rid;
|
|
u32 capability;
|
|
};
|
|
|
|
static const struct ras_DID_capability supported_DID_array[] = {
|
|
{0x66a0, 0x00, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a0, 0x02, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a1, 0x00, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a1, 0x01, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a1, 0x04, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a3, 0x00, AMDGPU_RAS_BLOCK_MASK},
|
|
{0x66a7, 0x00, AMDGPU_RAS_BLOCK_MASK},
|
|
};
|
|
|
|
static uint32_t amdgpu_ras_check_supported(struct amdgpu_device *adev)
|
|
{
|
|
/* TODO need check vbios table */
|
|
int i;
|
|
int did = adev->pdev->device;
|
|
int rid = adev->pdev->revision;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(supported_DID_array); i++) {
|
|
if (did == supported_DID_array[i].did &&
|
|
rid == supported_DID_array[i].rid) {
|
|
return supported_DID_array[i].capability;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_init(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
uint32_t supported = amdgpu_ras_check_supported(adev);
|
|
|
|
if (con || supported == 0)
|
|
return 0;
|
|
|
|
con = kmalloc(sizeof(struct amdgpu_ras) +
|
|
sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
|
|
GFP_KERNEL|__GFP_ZERO);
|
|
if (!con)
|
|
return -ENOMEM;
|
|
|
|
con->objs = (struct ras_manager *)(con + 1);
|
|
|
|
amdgpu_ras_set_context(adev, con);
|
|
|
|
con->supported = supported;
|
|
con->features = 0;
|
|
INIT_LIST_HEAD(&con->head);
|
|
|
|
if (amdgpu_ras_recovery_init(adev))
|
|
goto recovery_out;
|
|
|
|
amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
|
|
|
|
amdgpu_ras_enable_all_features(adev, 1);
|
|
|
|
if (amdgpu_ras_fs_init(adev))
|
|
goto fs_out;
|
|
|
|
amdgpu_ras_self_test(adev);
|
|
return 0;
|
|
fs_out:
|
|
amdgpu_ras_recovery_fini(adev);
|
|
recovery_out:
|
|
amdgpu_ras_set_context(adev, NULL);
|
|
kfree(con);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* do some fini work before IP fini as dependence */
|
|
int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
|
|
if (!con)
|
|
return 0;
|
|
|
|
/* Need disable ras on all IPs here before ip [hw/sw]fini */
|
|
amdgpu_ras_disable_all_features(adev, 0);
|
|
amdgpu_ras_recovery_fini(adev);
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_ras_fini(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
|
|
|
if (!con)
|
|
return 0;
|
|
|
|
amdgpu_ras_fs_fini(adev);
|
|
amdgpu_ras_interrupt_remove_all(adev);
|
|
|
|
WARN(con->features, "Feature mask is not cleared");
|
|
|
|
if (con->features)
|
|
amdgpu_ras_disable_all_features(adev, 1);
|
|
|
|
amdgpu_ras_set_context(adev, NULL);
|
|
kfree(con);
|
|
|
|
return 0;
|
|
}
|