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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a99631489b
Now only the virtual addresses [0xf4000000, 0xf5ffffff] are used for static per-SoC mappings. The few mappings of whole chip selects are moved accordingly. The now wrong defines for virtual base addresses are removed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
257 lines
9.7 KiB
C
257 lines
9.7 KiB
C
/*
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* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
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* - Platform specific register memory map
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*
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* Copyright 2005-2007 Motorola, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_MXC91231_H__
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#define __MACH_MXC91231_H__
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/*
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* L2CC
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*/
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#define MXC91231_L2CC_BASE_ADDR 0x30000000
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#define MXC91231_L2CC_SIZE SZ_64K
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/*
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* AIPS 1
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*/
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#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
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#define MXC91231_AIPS1_SIZE SZ_1M
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#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
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#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
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#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
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#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
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#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
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#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
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#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
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#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
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#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
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#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
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#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
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#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
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#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
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#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
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#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
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#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
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#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
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/*
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* AIPS 2
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*/
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#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
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#define MXC91231_AIPS2_SIZE SZ_1M
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#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
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#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
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#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
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#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
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#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
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#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
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#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
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#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
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#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
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#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
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#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
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#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
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#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
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#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
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#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
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#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
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#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
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#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
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/*
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* SPBA global module 0
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*/
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#define MXC91231_SPBA0_BASE_ADDR 0x50000000
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#define MXC91231_SPBA0_SIZE SZ_1M
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#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
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#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
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#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
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#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
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#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
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#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
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#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
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#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
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#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
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#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
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#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
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#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
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#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
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#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
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#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
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#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
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#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
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#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
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#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
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#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
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#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
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#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
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/*
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* SPBA global module 1
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*/
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#define MXC91231_SPBA1_BASE_ADDR 0x52000000
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#define MXC91231_SPBA1_SIZE SZ_1M
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#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
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#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
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/*!
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* Defines for SPBA modules
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*/
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#define MXC91231_SPBA_SDHC1 0x04
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#define MXC91231_SPBA_SDHC2 0x08
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#define MXC91231_SPBA_UART3 0x0C
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#define MXC91231_SPBA_CSPI2 0x10
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#define MXC91231_SPBA_SSI2 0x14
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#define MXC91231_SPBA_SIM 0x18
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#define MXC91231_SPBA_IIM 0x1C
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#define MXC91231_SPBA_CTI_SDMA 0x20
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#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
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#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
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#define MXC91231_SPBA_CSPI1 0x30
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#define MXC91231_SPBA_MQSPI 0x34
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#define MXC91231_SPBA_EL1T 0x38
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#define MXC91231_SPBA_IOMUX 0x40
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#define MXC91231_SPBA_CRM_COM 0x44
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#define MXC91231_SPBA_CRM_AP 0x48
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#define MXC91231_SPBA_PLL0 0x4C
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#define MXC91231_SPBA_PLL1 0x50
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#define MXC91231_SPBA_PLL2 0x54
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#define MXC91231_SPBA_GPIO4 0x58
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#define MXC91231_SPBA_SAHARA 0x5C
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/*
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* ROMP and AVIC
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*/
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#define MXC91231_ROMP_BASE_ADDR 0x60000000
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#define MXC91231_ROMP_SIZE SZ_64K
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#define MXC91231_AVIC_BASE_ADDR 0x68000000
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#define MXC91231_AVIC_SIZE SZ_64K
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
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#define MXC91231_X_MEMC_SIZE SZ_64K
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#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
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#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
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#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
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#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
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#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
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/*
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* Memory regions and CS
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* CPLD is connected on CS4
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* CS5 is TP1021 or it is not connected
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* */
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#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
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#define MXC91231_FB_RAM_SIZE SZ_256K
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#define MXC91231_CSD0_BASE_ADDR 0x80000000
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#define MXC91231_CSD1_BASE_ADDR 0x90000000
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#define MXC91231_CS0_BASE_ADDR 0xA0000000
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#define MXC91231_CS1_BASE_ADDR 0xA8000000
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#define MXC91231_CS2_BASE_ADDR 0xB0000000
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#define MXC91231_CS3_BASE_ADDR 0xB2000000
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#define MXC91231_CS4_BASE_ADDR 0xB4000000
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#define MXC91231_CS5_BASE_ADDR 0xB6000000
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/*
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* This macro defines the physical to virtual address mapping for all the
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* peripheral modules. It is used by passing in the physical address as x
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* and returning the virtual address.
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*/
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#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
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#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
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/*
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* Interrupt numbers
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*/
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#define MXC91231_INT_GPIO3 0
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#define MXC91231_INT_EL1T_CI 1
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#define MXC91231_INT_EL1T_RFCI 2
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#define MXC91231_INT_EL1T_RFI 3
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#define MXC91231_INT_EL1T_MCU 4
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#define MXC91231_INT_EL1T_IPI 5
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#define MXC91231_INT_MU_GEN 6
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#define MXC91231_INT_GPIO4 7
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#define MXC91231_INT_MMC_SDHC2 8
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#define MXC91231_INT_MMC_SDHC1 9
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#define MXC91231_INT_I2C 10
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#define MXC91231_INT_SSI2 11
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#define MXC91231_INT_SSI1 12
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#define MXC91231_INT_CSPI2 13
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#define MXC91231_INT_CSPI1 14
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#define MXC91231_INT_RTIC 15
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#define MXC91231_INT_SAHARA 15
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#define MXC91231_INT_HAC 15
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#define MXC91231_INT_UART3_RX 16
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#define MXC91231_INT_UART3_TX 17
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#define MXC91231_INT_UART3_MINT 18
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#define MXC91231_INT_ECT 19
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#define MXC91231_INT_SIM_IPB 20
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#define MXC91231_INT_SIM_DATA 21
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#define MXC91231_INT_RNGA 22
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#define MXC91231_INT_DSM_AP 23
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#define MXC91231_INT_KPP 24
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#define MXC91231_INT_RTC 25
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#define MXC91231_INT_PWM 26
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#define MXC91231_INT_GEMK_AP 27
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#define MXC91231_INT_EPIT 28
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#define MXC91231_INT_GPT 29
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#define MXC91231_INT_UART2_RX 30
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#define MXC91231_INT_UART2_TX 31
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#define MXC91231_INT_UART2_MINT 32
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#define MXC91231_INT_NANDFC 33
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#define MXC91231_INT_SDMA 34
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#define MXC91231_INT_USB_WAKEUP 35
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#define MXC91231_INT_USB_SOF 36
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#define MXC91231_INT_PMU_EVTMON 37
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#define MXC91231_INT_USB_FUNC 38
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#define MXC91231_INT_USB_DMA 39
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#define MXC91231_INT_USB_CTRL 40
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#define MXC91231_INT_IPU_ERR 41
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#define MXC91231_INT_IPU_SYN 42
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#define MXC91231_INT_UART1_RX 43
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#define MXC91231_INT_UART1_TX 44
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#define MXC91231_INT_UART1_MINT 45
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#define MXC91231_INT_IIM 46
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#define MXC91231_INT_MU_RX_OR 47
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#define MXC91231_INT_MU_TX_OR 48
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#define MXC91231_INT_SCC_SCM 49
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#define MXC91231_INT_SCC_SMN 50
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#define MXC91231_INT_GPIO2 51
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#define MXC91231_INT_GPIO1 52
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#define MXC91231_INT_MQSPI1 53
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#define MXC91231_INT_MQSPI2 54
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#define MXC91231_INT_WDOG2 55
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#define MXC91231_INT_EXT_INT7 56
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#define MXC91231_INT_EXT_INT6 57
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#define MXC91231_INT_EXT_INT5 58
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#define MXC91231_INT_EXT_INT4 59
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#define MXC91231_INT_EXT_INT3 60
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#define MXC91231_INT_EXT_INT2 61
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#define MXC91231_INT_EXT_INT1 62
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#define MXC91231_INT_EXT_INT0 63
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#define MXC91231_MAX_INT_LINES 63
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#define MXC91231_MAX_EXT_LINES 8
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#endif /* __MACH_MXC91231_H__ */
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