Francisco Jerez 965fd602a6 drm/i915: Make sure DC writes are coherent on flush. ... We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee that writes performed via the HDC are visible in memory. Fixes an intermittent failure in a Piglit test that writes to a BO from a shader using GL atomic counters (implemented as HDC untyped atomics) and then expects the memory to read back the same value after mapping it on the CPU. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298 Tested-by: Mark Janes <mark.a.janes@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452740379-3194-1-git-send-email-currojerez@riseup.net Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2016-01-15 11:33:52 +02:00
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drm	drm/i915: Make sure DC writes are coherent on flush.	2016-01-15 11:33:52 +02:00
host1x
ipu-v3	gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports	2015-11-24 11:30:17 +01:00
vga	vga_switcheroo: Drop client power state VGA_SWITCHEROO_INIT	2015-11-05 11:07:36 +10:00
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