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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 15:36:10 +07:00
b54fcf6ae1
There are a few defines that manully shift a bit. Change these to using the BIT() macro. Signed-off-by: John Crispin <john@phrozen.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15322/ Signed-off-by: James Hogan <jhogan@kernel.org>
423 lines
9.8 KiB
C
423 lines
9.8 KiB
C
/*
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* Ralink MT7620A SoC PCI support
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*
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* Copyright (C) 2007-2013 Bruce Chang (Mediatek)
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* Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#define RALINK_PCI_IO_MAP_BASE 0x10160000
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#define RALINK_PCI_MEMORY_BASE 0x0
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#define RALINK_INT_PCIE0 4
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#define RALINK_CLKCFG1 0x30
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#define RALINK_GPIOMODE 0x60
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#define PPLL_CFG1 0x9c
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#define PPLL_DRV 0xa0
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#define PDRV_SW_SET BIT(31)
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#define LC_CKDRVPD BIT(19)
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#define LC_CKDRVOHZ BIT(18)
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#define LC_CKDRVHZ BIT(17)
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#define LC_CKTEST BIT(16)
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/* PCI Bridge registers */
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#define RALINK_PCI_PCICFG_ADDR 0x00
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#define PCIRST BIT(1)
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#define RALINK_PCI_PCIENA 0x0C
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#define PCIINT2 BIT(20)
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#define RALINK_PCI_CONFIG_ADDR 0x20
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#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
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#define RALINK_PCI_MEMBASE 0x28
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#define RALINK_PCI_IOBASE 0x2C
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/* PCI RC registers */
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#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
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#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
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#define RALINK_PCI0_ID 0x30
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#define RALINK_PCI0_CLASS 0x34
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#define RALINK_PCI0_SUBID 0x38
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#define RALINK_PCI0_STATUS 0x50
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#define PCIE_LINK_UP_ST BIT(0)
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#define PCIEPHY0_CFG 0x90
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#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
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#define RALINK_PCIE0_CLK_EN BIT(26)
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#define BUSY 0x80000000
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#define WAITRETRY_MAX 10
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#define WRITE_MODE (1UL << 23)
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#define DATA_SHIFT 0
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#define ADDR_SHIFT 8
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static void __iomem *bridge_base;
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static void __iomem *pcie_base;
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static struct reset_control *rstpcie0;
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static inline void bridge_w32(u32 val, unsigned reg)
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{
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iowrite32(val, bridge_base + reg);
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}
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static inline u32 bridge_r32(unsigned reg)
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{
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return ioread32(bridge_base + reg);
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}
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static inline void pcie_w32(u32 val, unsigned reg)
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{
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iowrite32(val, pcie_base + reg);
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}
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static inline u32 pcie_r32(unsigned reg)
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{
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return ioread32(pcie_base + reg);
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}
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static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
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{
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u32 val = pcie_r32(reg);
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val &= ~clr;
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val |= set;
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pcie_w32(val, reg);
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}
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static int wait_pciephy_busy(void)
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{
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unsigned long reg_value = 0x0, retry = 0;
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while (1) {
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reg_value = pcie_r32(PCIEPHY0_CFG);
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if (reg_value & BUSY)
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mdelay(100);
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else
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break;
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if (retry++ > WAITRETRY_MAX) {
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pr_warn("PCIE-PHY retry failed.\n");
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return -1;
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}
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}
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return 0;
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}
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static void pcie_phy(unsigned long addr, unsigned long val)
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{
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wait_pciephy_busy();
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pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
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PCIEPHY0_CFG);
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mdelay(1);
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wait_pciephy_busy();
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned int slot = PCI_SLOT(devfn);
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u8 func = PCI_FUNC(devfn);
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u32 address;
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u32 data;
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u32 num = 0;
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if (bus)
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num = bus->number;
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address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
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(func << 8) | (where & 0xfc) | 0x80000000;
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bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
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data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned int slot = PCI_SLOT(devfn);
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u8 func = PCI_FUNC(devfn);
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u32 address;
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u32 data;
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u32 num = 0;
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if (bus)
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num = bus->number;
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address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
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(func << 8) | (where & 0xfc) | 0x80000000;
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bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
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data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
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switch (size) {
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case 1:
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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data = val;
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break;
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}
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bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops mt7620_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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static struct resource mt7620_res_pci_mem1;
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static struct resource mt7620_res_pci_io1;
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struct pci_controller mt7620_controller = {
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.pci_ops = &mt7620_pci_ops,
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.mem_resource = &mt7620_res_pci_mem1,
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.mem_offset = 0x00000000UL,
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.io_resource = &mt7620_res_pci_io1,
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.io_offset = 0x00000000UL,
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.io_map_base = 0xa0000000,
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};
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static int mt7620_pci_hw_init(struct platform_device *pdev)
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{
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/* bypass PCIe DLL */
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pcie_phy(0x0, 0x80);
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pcie_phy(0x1, 0x04);
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/* Elastic buffer control */
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pcie_phy(0x68, 0xB4);
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/* put core into reset */
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pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
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reset_control_assert(rstpcie0);
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/* disable power and all clocks */
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
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/* bring core out of reset */
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reset_control_deassert(rstpcie0);
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rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
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mdelay(100);
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if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
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dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
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reset_control_assert(rstpcie0);
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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return -1;
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}
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/* power up the bus */
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rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
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PPLL_DRV);
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return 0;
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}
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static int mt7628_pci_hw_init(struct platform_device *pdev)
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{
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u32 val = 0;
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/* bring the core out of reset */
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rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
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reset_control_deassert(rstpcie0);
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/* enable the pci clk */
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rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
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mdelay(100);
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/* voodoo from the SDK driver */
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pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
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pci_config_read(NULL, 0, 0x70c, 4, &val);
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val &= ~(0xff) << 8;
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val |= 0x50 << 8;
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pci_config_write(NULL, 0, 0x70c, 4, val);
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pci_config_read(NULL, 0, 0x70c, 4, &val);
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dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
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return 0;
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}
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static int mt7620_pci_probe(struct platform_device *pdev)
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{
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struct resource *bridge_res = platform_get_resource(pdev,
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IORESOURCE_MEM, 0);
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struct resource *pcie_res = platform_get_resource(pdev,
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IORESOURCE_MEM, 1);
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u32 val = 0;
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rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
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if (IS_ERR(rstpcie0))
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return PTR_ERR(rstpcie0);
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bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
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if (IS_ERR(bridge_base))
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return PTR_ERR(bridge_base);
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pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
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if (IS_ERR(pcie_base))
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return PTR_ERR(pcie_base);
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iomem_resource.start = 0;
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iomem_resource.end = ~0;
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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/* bring up the pci core */
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switch (ralink_soc) {
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case MT762X_SOC_MT7620A:
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if (mt7620_pci_hw_init(pdev))
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return -1;
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break;
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case MT762X_SOC_MT7628AN:
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if (mt7628_pci_hw_init(pdev))
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return -1;
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break;
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default:
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dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
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return -1;
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}
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mdelay(50);
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/* enable write access */
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pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
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mdelay(100);
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/* check if there is a card present */
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if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
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reset_control_assert(rstpcie0);
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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if (ralink_soc == MT762X_SOC_MT7620A)
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rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
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dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
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return -1;
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}
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/* setup ranges */
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bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
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bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
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pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
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pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
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pcie_w32(0x06040001, RALINK_PCI0_CLASS);
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/* enable interrupts */
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pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
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/* voodoo from the SDK driver */
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pci_config_read(NULL, 0, 4, 4, &val);
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pci_config_write(NULL, 0, 4, 4, val | 0x7);
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pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
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register_pci_controller(&mt7620_controller);
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return 0;
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}
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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u16 cmd;
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u32 val;
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int irq = 0;
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if ((dev->bus->number == 0) && (slot == 0)) {
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pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
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pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
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RALINK_PCI_MEMORY_BASE);
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pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
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} else if ((dev->bus->number == 1) && (slot == 0x0)) {
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irq = RALINK_INT_PCIE0;
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} else {
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dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
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dev->bus->number, slot);
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return 0;
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}
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dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
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dev->bus->number, slot, irq);
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/* configure the cache line size to 0x14 */
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
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/* configure latency timer to 0xff */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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/* setup the slot */
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cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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return irq;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static const struct of_device_id mt7620_pci_ids[] = {
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{ .compatible = "mediatek,mt7620-pci" },
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{},
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};
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static struct platform_driver mt7620_pci_driver = {
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.probe = mt7620_pci_probe,
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.driver = {
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.name = "mt7620-pci",
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.of_match_table = of_match_ptr(mt7620_pci_ids),
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},
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};
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static int __init mt7620_pci_init(void)
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{
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return platform_driver_register(&mt7620_pci_driver);
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}
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arch_initcall(mt7620_pci_init);
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