Guo Ren 96354ad79e csky: fixup CACHEV1 store instruction fast retire ... For I/O access, 810/807 store instruction fast retire will cause wrong primitive. For example: stw (clear interrupt source) stw (unmask interrupt controller) enable interrupt stw is fast retire instruction. When PC is run at enable interrupt stage, the clear interrupt source hasn't finished. It will cause another wrong irq-enter. So use mb() to prevent above. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Lu Baoquan <lu.baoquan@intellif.com>		2019-01-08 23:42:42 +08:00
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abiv1	arch/csky patches for 4.21-rc1	2019-01-05 09:50:07 -08:00
abiv2	csky: ftrace call graph supported.	2018-12-31 23:17:23 +08:00
boot	csky: use common dtb build rules	2018-11-01 10:52:27 +08:00
configs	csky: defconfig	2018-10-25 23:36:19 +08:00
include	csky: fixup CACHEV1 store instruction fast retire	2019-01-08 23:42:42 +08:00
kernel	csky: fixup relocation error with 807 & 860	2019-01-08 19:52:22 +08:00
lib	Remove 'type' argument from access_ok() function	2019-01-03 18:57:57 -08:00
mm	arch/csky patches for 4.21-rc1	2019-01-05 09:50:07 -08:00
Kconfig	arch/csky patches for 4.21-rc1	2019-01-05 09:50:07 -08:00
Kconfig.debug	csky: remove builtin-dtb Kbuild	2018-11-01 10:52:26 +08:00
Makefile	csky: stacktrace supported.	2018-12-31 23:12:22 +08:00