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8d94cc50aa
Stabilize PIO mode transfers against a range of word sizes and FIFO thresholds and fixes word size setup/override issues. 1) 16 and 32 bit DMA/PIO transfers broken due to timing differences. 2) Potential for bad transfer counts due to transfer size assumptions. 3) Setup function broken is multiple ways. 4) Per transfer bit_per_word changes break DMA setup in pump_tranfers. 5) False positive timeout are not errors. 6) Changes in pxa2xx_spi_chip not effective in calls to setup. 7) Timeout scaling wrong for PXA255 NSSP. 8) Driver leaks memory while busy during unloading. Known issues: SPI_CS_HIGH and SPI_LSB_FIRST settings in struct spi_device are not handled. Testing: This patch has been test against the "random length, random bits/word, random data (verified on loopback) and stepped baud rate by octaves (3.6MHz to 115kHz)" test. It is robust in PIO mode, using any combination of tx and rx thresholds, and also in DMA mode (which internally computes the thresholds). Much thanks to Ned Forrester for exhaustive reviews, fixes and testing. The driver is substantially better for his efforts. Signed-off-by: Stephen Street <stephen@streetfiresound.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
235 lines
8.3 KiB
Plaintext
235 lines
8.3 KiB
Plaintext
PXA2xx SPI on SSP driver HOWTO
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===================================================
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This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into a SPI master controller
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(see Documentation/spi/spi_summary). The driver has the following features
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- Support for any PXA2xx SSP
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- SSP PIO and SSP DMA data transfers.
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- External and Internal (SSPFRM) chip selects.
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- Per slave device (chip) configuration.
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- Full suspend, freeze, resume support.
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The driver is built around a "spi_message" fifo serviced by workqueue and a
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tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
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(pump_transfer) is responsible for queuing SPI transactions and setting up and
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launching the dma/interrupt driven transfers.
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Declaring PXA2xx Master Controllers
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-----------------------------------
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Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
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"platform device". The master configuration is passed to the driver via a table
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found in include/asm-arm/arch-pxa/pxa2xx_spi.h:
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struct pxa2xx_spi_master {
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enum pxa_ssp_type ssp_type;
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u32 clock_enable;
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u16 num_chipselect;
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u8 enable_dma;
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};
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The "pxa2xx_spi_master.ssp_type" field must have a value between 1 and 3 and
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informs the driver which features a particular SSP supports.
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The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
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corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
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the "PXA2xx Developer Manual" section "Clocks and Power Management".
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The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
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slave device (chips) attached to this SPI master.
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The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
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be used. This caused the driver to acquire two DMA channels: rx_channel and
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tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
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See the "PXA2xx Developer Manual" section "DMA Controller".
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NSSP MASTER SAMPLE
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------------------
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Below is a sample configuration using the PXA255 NSSP.
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static struct resource pxa_spi_nssp_resources[] = {
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[0] = {
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.start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
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.end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_NSSP, /* NSSP IRQ */
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.end = IRQ_NSSP,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct pxa2xx_spi_master pxa_nssp_master_info = {
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.ssp_type = PXA25x_NSSP, /* Type of SSP */
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.clock_enable = CKEN9_NSSP, /* NSSP Peripheral clock */
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.num_chipselect = 1, /* Matches the number of chips attached to NSSP */
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.enable_dma = 1, /* Enables NSSP DMA */
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};
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static struct platform_device pxa_spi_nssp = {
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.name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
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.id = 2, /* Bus number, MUST MATCH SSP number 1..n */
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.resource = pxa_spi_nssp_resources,
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.num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
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.dev = {
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.platform_data = &pxa_nssp_master_info, /* Passed to driver */
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},
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};
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static struct platform_device *devices[] __initdata = {
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&pxa_spi_nssp,
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};
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static void __init board_init(void)
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{
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(void)platform_add_device(devices, ARRAY_SIZE(devices));
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}
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Declaring Slave Devices
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-----------------------
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Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
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using the "spi_board_info" structure found in "linux/spi/spi.h". See
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"Documentation/spi/spi_summary" for additional information.
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Each slave device attached to the PXA must provide slave specific configuration
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information via the structure "pxa2xx_spi_chip" found in
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"include/asm-arm/arch-pxa/pxa2xx_spi.h". The pxa2xx_spi master controller driver
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will uses the configuration whenever the driver communicates with the slave
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device.
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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u8 enable_loopback;
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void (*cs_control)(u32 command);
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};
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The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
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used to configure the SSP hardware fifo. These fields are critical to the
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performance of pxa2xx_spi driver and misconfiguration will result in rx
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fifo overruns (especially in PIO mode transfers). Good default values are
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.tx_threshold = 12,
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.rx_threshold = 4,
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The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
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engine and is related the "spi_device.bits_per_word" field. Read and understand
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the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
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to determine the correct value. An SSP configured for byte-wide transfers would
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use a value of 8.
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The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
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trailing bytes in the SSP receiver fifo. The correct value for this field is
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dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
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slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
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timeouts and must busy-wait any trailing bytes.
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The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
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into internal loopback mode. In this mode the SSP controller internally
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connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
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testing.
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The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
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function for asserting/deasserting a slave device chip select. If the field is
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NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
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configured to use SSPFRM instead.
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NSSP SALVE SAMPLE
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-----------------
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The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
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"spi_board_info.controller_data" field. Below is a sample configuration using
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the PXA255 NSSP.
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/* Chip Select control for the CS8415A SPI slave device */
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static void cs8415a_cs_control(u32 command)
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{
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if (command & PXA2XX_CS_ASSERT)
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GPCR(2) = GPIO_bit(2);
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else
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GPSR(2) = GPIO_bit(2);
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}
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/* Chip Select control for the CS8405A SPI slave device */
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static void cs8405a_cs_control(u32 command)
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{
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if (command & PXA2XX_CS_ASSERT)
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GPCR(3) = GPIO_bit(3);
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else
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GPSR(3) = GPIO_bit(3);
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}
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static struct pxa2xx_spi_chip cs8415a_chip_info = {
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.tx_threshold = 8, /* SSP hardward FIFO threshold */
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.rx_threshold = 8, /* SSP hardward FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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.cs_control = cs8415a_cs_control, /* Use external chip select */
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};
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static struct pxa2xx_spi_chip cs8405a_chip_info = {
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.tx_threshold = 8, /* SSP hardward FIFO threshold */
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.rx_threshold = 8, /* SSP hardward FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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.cs_control = cs8405a_cs_control, /* Use external chip select */
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};
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static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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{
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.modalias = "cs8415a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 0, /* Framework chip select */
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.platform_data = NULL; /* No spi_driver specific config */
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.controller_data = &cs8415a_chip_info, /* Master chip config */
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.irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
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},
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{
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.modalias = "cs8405a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 1, /* Framework chip select */
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.controller_data = &cs8405a_chip_info, /* Master chip config */
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.irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
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},
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};
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static void __init streetracer_init(void)
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{
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spi_register_board_info(streetracer_spi_board_info,
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ARRAY_SIZE(streetracer_spi_board_info));
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}
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DMA and PIO I/O Support
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-----------------------
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The pxa2xx_spi driver support both DMA and interrupt driven PIO message
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transfers. The driver defaults to PIO mode and DMA transfers must enabled by
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setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and
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ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero. The DMA
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mode support both coherent and stream based DMA mappings.
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The following logic is used to determine the type of I/O to be used on
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a per "spi_transfer" basis:
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if !enable_dma or dma_burst_size == 0 then
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always use PIO transfers
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if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
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use coherent DMA mode
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if rx_buf and tx_buf are aligned on 8 byte boundary then
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use streaming DMA mode
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otherwise
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use PIO transfer
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THANKS TO
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---------
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David Brownell and others for mentoring the development of this driver.
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