Mathias Kresin 05454c1bde MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset ... According to the QCA u-boot source the "PCIE Phase Lock Loop Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the QCA955X and QCA956X at offset 0x10. Since the PCIE PLL config register is only defined for the AR724x fix only this value. The value is wrong since the day it was added and isn't used by any driver yet. Signed-off-by: Mathias Kresin <dev@kresin.me> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16048/ Signed-off-by: James Hogan <jhogan@kernel.org>		2018-03-14 15:18:41 +00:00
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ar71xx_regs.h	MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset	2018-03-14 15:18:41 +00:00
ar933x_uart.h	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
ath79_spi_platform.h	spi: spi-ath79: Add device tree support	2015-04-27 15:44:56 +01:00
ath79.h	irqchip/ath79-cpu: Move the CPU IRQ driver from arch/mips/ath79/	2016-02-17 13:47:19 +00:00
cpu-feature-overrides.h	MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0	2013-09-03 23:22:16 +02:00
irq.h	MIPS: ath79: add IRQ handling code for the QCA955X SoCs	2013-02-19 09:36:25 +01:00
kernel-entry-init.h	MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs	2011-01-18 19:30:24 +01:00