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The delay circuit used to support HS400 is calibrated based on two additional clocks. When these clocks are not available and FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on some platforms this doesn't work properly and below dump can be seen in the kernel log. mmc0: Reset 0x1 never completed. mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00001102 mmc0: sdhci: Blk size: 0x00004000 | Blk cnt: 0x00000000 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 mmc0: sdhci: Present: 0x01f80000 | Host ctl: 0x00000000 mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000002 mmc0: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 mmc0: sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000 mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc0: sdhci: Caps: 0x742dc8b2 | Caps_1: 0x00008007 mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc0: sdhci: Host ctl2: 0x00000000 mmc0: sdhci: ============================================ Add support for the additional calibration clocks to allow these platforms to be configured appropriately. Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org> Cc: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
59 lines
1.9 KiB
Plaintext
59 lines
1.9 KiB
Plaintext
* Qualcomm SDHCI controller (sdhci-msm)
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-msm driver.
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Required properties:
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- compatible: Should contain "qcom,sdhci-msm-v4".
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- reg: Base address and length of the register in the following order:
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- Host controller register map (required)
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- SD Core register map (required)
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- interrupts: Should contain an interrupt-specifiers for the interrupts:
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- Host controller interrupt (required)
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- pinctrl-names: Should contain only one value - "default".
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- pinctrl-0: Should specify pin control groups used for this controller.
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
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- clock-names: Should contain the following:
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"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
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"core" - SDC MMC clock (MCLK) (required)
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"bus" - SDCC bus voter clock (optional)
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"xo" - TCXO clock (optional)
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"cal" - reference clock for RCLK delay calibration (optional)
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"sleep" - sleep clock for RCLK delay calibration (optional)
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Example:
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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interrupts = <0 123 0>;
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bus-width = <8>;
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non-removable;
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vmmc-supply = <&pm8941_l20>;
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vqmmc-supply = <&pm8941_s3>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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};
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sdhc_2: sdhci@f98a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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interrupts = <0 125 0>;
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bus-width = <4>;
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cd-gpios = <&msmgpio 62 0x1>;
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vmmc-supply = <&pm8941_l21>;
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vqmmc-supply = <&pm8941_l13>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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};
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