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149ed3d404
For security reasons I stopped using gmail account and kernel address is now up-to-date alias to my personal address. People periodically send me emails to address which they found in source code of drivers, so this change reflects state where people can contact me. [ Added .mailmap entry as per Joe Perches - Linus ] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Joe Perches <joe@perches.com> Link: http://lkml.kernel.org/r/20200307104237.8199-1-pali@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* omap-secure.h: OMAP Secure infrastructure header.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
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* Copyright (C) 2013 Pali Rohár <pali@kernel.org>
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*/
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#ifndef OMAP_ARCH_OMAP_SECURE_H
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#define OMAP_ARCH_OMAP_SECURE_H
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#include <linux/types.h>
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/* Monitor error code */
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#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
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#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
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/* HAL API error codes */
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#define API_HAL_RET_VALUE_OK 0x00
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#define API_HAL_RET_VALUE_FAIL 0x01
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/* Secure HAL API flags */
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#define FLAG_START_CRITICAL 0x4
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#define FLAG_IRQFIQ_MASK 0x3
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#define FLAG_IRQ_ENABLE 0x2
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#define FLAG_FIQ_ENABLE 0x1
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#define NO_FLAG 0x0
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/* Maximum Secure memory storage size */
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#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
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#define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
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/* Secure low power HAL API index */
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#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
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#define OMAP4_HAL_SAVEHW_INDEX 0x1b
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#define OMAP4_HAL_SAVEALL_INDEX 0x1c
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#define OMAP4_HAL_SAVEGIC_INDEX 0x1d
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/* Secure Monitor mode APIs */
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#define OMAP4_MON_SCU_PWR_INDEX 0x108
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#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
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#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
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#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
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#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
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#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
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#define OMAP5_MON_AMBA_IF_INDEX 0x108
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#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
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/* Secure PPA(Primary Protected Application) APIs */
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#define OMAP4_PPA_L2_POR_INDEX 0x23
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#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
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#define AM43xx_PPA_SVC_PM_SUSPEND 0x71
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#define AM43xx_PPA_SVC_PM_RESUME 0x72
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/* Secure RX-51 PPA (Primary Protected Application) APIs */
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#define RX51_PPA_HWRNG 29
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#define RX51_PPA_L2_INVAL 40
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#define RX51_PPA_WRITE_ACR 42
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#ifndef __ASSEMBLER__
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extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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extern void omap_smccc_smc(u32 fn, u32 arg);
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extern void omap_smc1(u32 fn, u32 arg);
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extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
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extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
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extern phys_addr_t omap_secure_ram_mempool_base(void);
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extern int omap_secure_ram_reserve_memblock(void);
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extern u32 save_secure_ram_context(u32 args_pa);
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extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
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extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4);
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extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
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extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
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extern bool optee_available;
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void omap_secure_init(void);
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#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
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void set_cntfreq(void);
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#else
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static inline void set_cntfreq(void)
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{
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}
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#endif
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#endif /* __ASSEMBLER__ */
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#endif /* OMAP_ARCH_OMAP_SECURE_H */
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