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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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95c27ba7bd
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal data is including the cpu and gpu sensor zone node. The thermal zone node is the node containing all the required info for describing a thermal zone, including its cooling device bindings. The thermal zone node must contain, apart from its own properties, one sub-node containing trip nodes and one sub-node containing all the zone cooling maps. The following is the parameter is introduced: * polling-delay: The maximum number of milliseconds to wait between polls * polling-delay-passive: The maximum number of milliseconds to wait between polls when performing passive cooling. * trips: A sub-node which is a container of only trip point nodes required to describe the thermal zone. * cooling-maps: A sub-node which is a container of only cooling device map nodes, used to describe the relation between trips and cooling devices. * cooling-device: A phandle of a cooling device with its specifier, referring to which cooling device is used in this cooling specifier binding. In the cooling specifier, the first cell is the minimum cooling state and the second cell is the maximum cooling state used in this map. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1164 lines
27 KiB
Plaintext
1164 lines
27 KiB
Plaintext
/*
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* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3399";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_l0>;
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};
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core1 {
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cpu = <&cpu_l1>;
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};
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core2 {
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cpu = <&cpu_l2>;
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};
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core3 {
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cpu = <&cpu_l3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_b0>;
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};
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core1 {
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cpu = <&cpu_b1>;
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};
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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clocks = <&cru ARMCLKL>;
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};
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cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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};
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cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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};
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cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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};
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cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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clocks = <&cru ARMCLKB>;
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};
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cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac_bus: dma-controller@ff6d0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6d0000 0x0 0x4000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC0_PERILP>;
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clock-names = "apb_pclk";
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};
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dmac_peri: dma-controller@ff6e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff6e0000 0x0 0x4000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1_PERILP>;
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clock-names = "apb_pclk";
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};
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};
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sdio0: dwmmc@fe310000 {
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compatible = "rockchip,rk3399-dw-mshc",
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"rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe310000 0x0 0x4000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdmmc: dwmmc@fe320000 {
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compatible = "rockchip,rk3399-dw-mshc",
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"rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe320000 0x0 0x4000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdhci: sdhci@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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status = "disabled";
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};
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usb_host0_ehci: usb@fe380000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
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clock-names = "hclk_host0", "hclk_host0_arb";
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status = "disabled";
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};
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usb_host0_ohci: usb@fe3a0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3a0000 0x0 0x20000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
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clock-names = "hclk_host0", "hclk_host0_arb";
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status = "disabled";
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};
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usb_host1_ehci: usb@fe3c0000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe3c0000 0x0 0x20000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
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clock-names = "hclk_host1", "hclk_host1_arb";
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status = "disabled";
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};
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usb_host1_ohci: usb@fe3e0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3e0000 0x0 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
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clock-names = "hclk_host1", "hclk_host1_arb";
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status = "disabled";
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};
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gic: interrupt-controller@fee00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
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<0x0 0xfef00000 0 0xc0000>, /* GICR */
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<0x0 0xfff00000 0 0x10000>, /* GICC */
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<0x0 0xfff10000 0 0x10000>, /* GICH */
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<0x0 0xfff20000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: interrupt-controller@fee20000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xfee20000 0x0 0x20000>;
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};
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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status = "disabled";
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};
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uart1: serial@ff190000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff190000 0x0 0x100>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart2: serial@ff1a0000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff1a0000 0x0 0x100>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2c_xfer>;
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status = "disabled";
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};
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uart3: serial@ff1b0000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff1b0000 0x0 0x100>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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};
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spi0: spi@ff1c0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff1c0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@ff1d0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff1d0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@ff1e0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff1e0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@ff1f0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff1f0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@ff200000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff200000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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thermal-zones {
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cpu_thermal: cpu {
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polling-delay-passive = <100>;
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polling-delay = <1000>;
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thermal-sensors = <&tsadc 0>;
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trips {
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cpu_alert0: cpu_alert0 {
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temperature = <70000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu_thermal: gpu {
|
|
polling-delay-passive = <100>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsadc 1>;
|
|
|
|
trips {
|
|
gpu_alert0: gpu_alert0 {
|
|
temperature = <75000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
gpu_crit: gpu_crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu_alert0>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tsadc: tsadc@ff260000 {
|
|
compatible = "rockchip,rk3399-tsadc";
|
|
reg = <0x0 0xff260000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
assigned-clocks = <&cru SCLK_TSADC>;
|
|
assigned-clock-rates = <750000>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,hw-tshut-temp = <95000>;
|
|
pinctrl-names = "init", "default", "sleep";
|
|
pinctrl-0 = <&otp_gpio>;
|
|
pinctrl-1 = <&otp_out>;
|
|
pinctrl-2 = <&otp_gpio>;
|
|
#thermal-sensor-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmugrf: syscon@ff320000 {
|
|
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff320000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pmu_io_domains: io-domains {
|
|
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spi3: spi@ff350000 {
|
|
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff350000 0x0 0x1000>;
|
|
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@ff370000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff370000 0x0 0x100>;
|
|
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff420000 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff420010 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff420020 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff420030 {
|
|
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff420030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3a_pin>;
|
|
clocks = <&pmucru PCLK_RKPWM_PMU>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pmucru: pmu-clock-controller@ff750000 {
|
|
compatible = "rockchip,rk3399-pmucru";
|
|
reg = <0x0 0xff750000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks = <&pmucru PLL_PPLL>;
|
|
assigned-clock-rates = <676000000>;
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3399-cru";
|
|
reg = <0x0 0xff760000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks =
|
|
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
|
<&cru PLL_NPLL>,
|
|
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
|
|
<&cru PCLK_PERIHP>,
|
|
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
|
|
<&cru PCLK_PERILP0>,
|
|
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
|
|
assigned-clock-rates =
|
|
<594000000>, <800000000>,
|
|
<1000000000>,
|
|
<150000000>, <75000000>,
|
|
<37500000>,
|
|
<100000000>, <100000000>,
|
|
<50000000>,
|
|
<100000000>, <50000000>;
|
|
};
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff770000 0x0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
io_domains: io-domains {
|
|
compatible = "rockchip,rk3399-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc_phy: phy@f780 {
|
|
compatible = "rockchip,rk3399-emmc-phy";
|
|
reg = <0xf780 0x24>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
watchdog@ff840000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0x0 0xff840000 0x0 0x100>;
|
|
clocks = <&cru PCLK_WDT>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spdif: spdif@ff870000 {
|
|
compatible = "rockchip,rk3399-spdif";
|
|
reg = <0x0 0xff870000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac_bus 7>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: i2s@ff880000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff880000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_8ch_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@ff890000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff890000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_2ch_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2: i2s@ff8a0000 {
|
|
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff8a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3399-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmugrf>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff720000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff720000 0x0 0x100>;
|
|
clocks = <&pmucru PCLK_GPIO0_PMU>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff730000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff730000 0x0 0x100>;
|
|
clocks = <&pmucru PCLK_GPIO1_PMU>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff780000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff780000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff788000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff788000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio4: gpio4@ff790000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff790000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
|
|
bias-pull-down;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
|
|
bias-pull-down;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_none_13ma: pcfg-pull-none-13ma {
|
|
bias-disable;
|
|
drive-strength = <13>;
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins =
|
|
<1 15 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 16 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins =
|
|
<4 2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins =
|
|
<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
|
|
<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins =
|
|
<4 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 16 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins =
|
|
<1 12 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins =
|
|
<3 11 RK_FUNC_2 &pcfg_pull_none>,
|
|
<3 10 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c6 {
|
|
i2c6_xfer: i2c6-xfer {
|
|
rockchip,pins =
|
|
<2 10 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 9 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c7 {
|
|
i2c7_xfer: i2c7-xfer {
|
|
rockchip,pins =
|
|
<2 8 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 7 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c8 {
|
|
i2c8_xfer: i2c8-xfer {
|
|
rockchip,pins =
|
|
<1 21 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_8ch_bus: i2s0-8ch-bus {
|
|
rockchip,pins =
|
|
<3 24 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 25 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 26 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 27 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 28 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 29 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 30 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 31 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_2ch_bus: i2s1-2ch-bus {
|
|
rockchip,pins =
|
|
<4 3 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 5 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<4 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_bus: spdif-bus {
|
|
rockchip,pins =
|
|
<4 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins =
|
|
<3 6 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins =
|
|
<3 7 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins =
|
|
<3 8 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins =
|
|
<3 5 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins =
|
|
<3 4 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins =
|
|
<1 9 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins =
|
|
<1 10 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins =
|
|
<1 7 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins =
|
|
<1 8 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins =
|
|
<2 11 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins =
|
|
<2 12 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins =
|
|
<2 9 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins =
|
|
<2 10 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi3 {
|
|
spi3_clk: spi3-clk {
|
|
rockchip,pins =
|
|
<1 17 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi3_cs0: spi3-cs0 {
|
|
rockchip,pins =
|
|
<1 18 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi3_rx: spi3-rx {
|
|
rockchip,pins =
|
|
<1 15 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi3_tx: spi3-tx {
|
|
rockchip,pins =
|
|
<1 16 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi4 {
|
|
spi4_clk: spi4-clk {
|
|
rockchip,pins =
|
|
<3 2 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi4_cs0: spi4-cs0 {
|
|
rockchip,pins =
|
|
<3 3 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi4_rx: spi4-rx {
|
|
rockchip,pins =
|
|
<3 0 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi4_tx: spi4-tx {
|
|
rockchip,pins =
|
|
<3 1 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi5 {
|
|
spi5_clk: spi5-clk {
|
|
rockchip,pins =
|
|
<2 22 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi5_cs0: spi5-cs0 {
|
|
rockchip,pins =
|
|
<2 23 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi5_rx: spi5-rx {
|
|
rockchip,pins =
|
|
<2 20 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi5_tx: spi5-tx {
|
|
rockchip,pins =
|
|
<2 21 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins =
|
|
<2 16 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins =
|
|
<2 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins =
|
|
<2 19 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins =
|
|
<3 12 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 13 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2a {
|
|
uart2a_xfer: uart2a-xfer {
|
|
rockchip,pins =
|
|
<4 8 RK_FUNC_2 &pcfg_pull_up>,
|
|
<4 9 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2b {
|
|
uart2b_xfer: uart2b-xfer {
|
|
rockchip,pins =
|
|
<4 16 RK_FUNC_2 &pcfg_pull_up>,
|
|
<4 17 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2c {
|
|
uart2c_xfer: uart2c-xfer {
|
|
rockchip,pins =
|
|
<4 19 RK_FUNC_1 &pcfg_pull_up>,
|
|
<4 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins =
|
|
<3 14 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 15 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins =
|
|
<3 18 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins =
|
|
<3 19 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins =
|
|
<1 7 RK_FUNC_1 &pcfg_pull_up>,
|
|
<1 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uarthdcp {
|
|
uarthdcp_xfer: uarthdcp-xfer {
|
|
rockchip,pins =
|
|
<4 21 RK_FUNC_2 &pcfg_pull_up>,
|
|
<4 22 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins =
|
|
<4 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
vop0_pwm_pin: vop0-pwm-pin {
|
|
rockchip,pins =
|
|
<4 18 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins =
|
|
<4 22 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
vop1_pwm_pin: vop1-pwm-pin {
|
|
rockchip,pins =
|
|
<4 18 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins =
|
|
<1 19 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3a {
|
|
pwm3a_pin: pwm3a-pin {
|
|
rockchip,pins =
|
|
<0 6 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3b {
|
|
pwm3b_pin: pwm3b-pin {
|
|
rockchip,pins =
|
|
<1 14 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|