mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 08:26:49 +07:00
701a5dc05a
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
126 lines
4.7 KiB
C
126 lines
4.7 KiB
C
/*======================================================================
|
|
|
|
Device driver for the PCMCIA control functionality of StrongARM
|
|
SA-1100 microprocessors.
|
|
|
|
The contents of this file are subject to the Mozilla Public
|
|
License Version 1.1 (the "License"); you may not use this file
|
|
except in compliance with the License. You may obtain a copy of
|
|
the License at http://www.mozilla.org/MPL/
|
|
|
|
Software distributed under the License is distributed on an "AS
|
|
IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
|
|
implied. See the License for the specific language governing
|
|
rights and limitations under the License.
|
|
|
|
The initial developer of the original code is John G. Dorsey
|
|
<john+@cs.cmu.edu>. Portions created by John G. Dorsey are
|
|
Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
|
|
|
|
Alternatively, the contents of this file may be used under the
|
|
terms of the GNU Public License version 2 (the "GPL"), in which
|
|
case the provisions of the GPL are applicable instead of the
|
|
above. If you wish to allow the use of your version of this file
|
|
only under the terms of the GPL and not to allow others to use
|
|
your version of this file under the MPL, indicate your decision
|
|
by deleting the provisions above and replace them with the notice
|
|
and other provisions required by the GPL. If you do not delete
|
|
the provisions above, a recipient may use your version of this
|
|
file under either the MPL or the GPL.
|
|
|
|
======================================================================*/
|
|
|
|
#if !defined(_PCMCIA_SA1100_H)
|
|
# define _PCMCIA_SA1100_H
|
|
|
|
/* SA-1100 PCMCIA Memory and I/O timing
|
|
* ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
* The SA-1110 Developer's Manual, section 10.2.5, says the following:
|
|
*
|
|
* "To calculate the recommended BS_xx value for each address space:
|
|
* divide the command width time (the greater of twIOWR and twIORD,
|
|
* or the greater of twWE and twOE) by processor cycle time; divide
|
|
* by 2; divide again by 3 (number of BCLK's per command assertion);
|
|
* round up to the next whole number; and subtract 1."
|
|
*/
|
|
|
|
/* MECR: Expansion Memory Configuration Register
|
|
* (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
|
|
*
|
|
* MECR layout is:
|
|
*
|
|
* FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
|
|
*
|
|
* (This layout is actually true only for the SA-1110; the FASTn bits are
|
|
* reserved on the SA-1100.)
|
|
*/
|
|
|
|
#define MECR_SOCKET_0_SHIFT (0)
|
|
#define MECR_SOCKET_1_SHIFT (16)
|
|
|
|
#define MECR_BS_MASK (0x1f)
|
|
#define MECR_FAST_MODE_MASK (0x01)
|
|
|
|
#define MECR_BSIO_SHIFT (0)
|
|
#define MECR_BSA_SHIFT (5)
|
|
#define MECR_BSM_SHIFT (10)
|
|
#define MECR_FAST_SHIFT (15)
|
|
|
|
#define MECR_SET(mecr, sock, shift, mask, bs) \
|
|
((mecr)=((mecr)&~(((mask)<<(shift))<<\
|
|
((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
|
|
(((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
|
|
|
|
#define MECR_GET(mecr, sock, shift, mask) \
|
|
((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
|
|
(shift))&(mask))
|
|
|
|
#define MECR_BSIO_SET(mecr, sock, bs) \
|
|
MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
|
|
|
|
#define MECR_BSIO_GET(mecr, sock) \
|
|
MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
|
|
|
|
#define MECR_BSA_SET(mecr, sock, bs) \
|
|
MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
|
|
|
|
#define MECR_BSA_GET(mecr, sock) \
|
|
MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
|
|
|
|
#define MECR_BSM_SET(mecr, sock, bs) \
|
|
MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
|
|
|
|
#define MECR_BSM_GET(mecr, sock) \
|
|
MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
|
|
|
|
#define MECR_FAST_SET(mecr, sock, fast) \
|
|
MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
|
|
|
|
#define MECR_FAST_GET(mecr, sock) \
|
|
MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
|
|
|
|
|
|
/* This function implements the BS value calculation for setting the MECR
|
|
* using integer arithmetic:
|
|
*/
|
|
static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
|
|
unsigned int cpu_clock_khz){
|
|
unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
|
|
return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
|
|
}
|
|
|
|
/* This function returns the (approximate) command assertion period, in
|
|
* nanoseconds, for a given CPU clock frequency and MECR BS value:
|
|
*/
|
|
static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
|
|
unsigned int pcmcia_mecr_bs){
|
|
return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10;
|
|
}
|
|
|
|
|
|
int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt);
|
|
void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops);
|
|
extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr);
|
|
|
|
#endif /* !defined(_PCMCIA_SA1100_H) */
|