mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 00:36:50 +07:00
ee71e5f1e7
The SHA1 digest is an array of 5 32-bit quantities, so we should refer
to them as such in order for this code to work correctly when built for
big endian. So replace 16 byte scalar loads and stores with 4x4 vector
ones where appropriate.
Fixes: 2c98833a42 ("arm64/crypto: SHA-1 using ARMv8 Crypto Extensions")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
151 lines
3.2 KiB
ArmAsm
151 lines
3.2 KiB
ArmAsm
/*
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* sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
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*
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* Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.arch armv8-a+crypto
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k0 .req v0
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k1 .req v1
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k2 .req v2
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k3 .req v3
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t0 .req v4
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t1 .req v5
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dga .req q6
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dgav .req v6
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dgb .req s7
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dgbv .req v7
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dg0q .req q12
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dg0s .req s12
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dg0v .req v12
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dg1s .req s13
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dg1v .req v13
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dg2s .req s14
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.macro add_only, op, ev, rc, s0, dg1
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.ifc \ev, ev
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add t1.4s, v\s0\().4s, \rc\().4s
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sha1h dg2s, dg0s
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.ifnb \dg1
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sha1\op dg0q, \dg1, t0.4s
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.else
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sha1\op dg0q, dg1s, t0.4s
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.endif
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.else
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.ifnb \s0
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add t0.4s, v\s0\().4s, \rc\().4s
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.endif
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sha1h dg1s, dg0s
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sha1\op dg0q, dg2s, t1.4s
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.endif
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.endm
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.macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
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sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
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add_only \op, \ev, \rc, \s1, \dg1
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sha1su1 v\s0\().4s, v\s3\().4s
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.endm
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/*
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* The SHA1 round constants
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*/
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.align 4
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.Lsha1_rcon:
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.word 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
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/*
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* void sha1_ce_transform(struct sha1_ce_state *sst, u8 const *src,
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* int blocks)
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*/
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ENTRY(sha1_ce_transform)
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/* load round constants */
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adr x6, .Lsha1_rcon
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ld1r {k0.4s}, [x6], #4
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ld1r {k1.4s}, [x6], #4
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ld1r {k2.4s}, [x6], #4
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ld1r {k3.4s}, [x6]
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/* load state */
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ld1 {dgav.4s}, [x0]
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ldr dgb, [x0, #16]
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/* load sha1_ce_state::finalize */
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ldr w4, [x0, #:lo12:sha1_ce_offsetof_finalize]
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/* load input */
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0: ld1 {v8.4s-v11.4s}, [x1], #64
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sub w2, w2, #1
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CPU_LE( rev32 v8.16b, v8.16b )
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CPU_LE( rev32 v9.16b, v9.16b )
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CPU_LE( rev32 v10.16b, v10.16b )
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CPU_LE( rev32 v11.16b, v11.16b )
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1: add t0.4s, v8.4s, k0.4s
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mov dg0v.16b, dgav.16b
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add_update c, ev, k0, 8, 9, 10, 11, dgb
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add_update c, od, k0, 9, 10, 11, 8
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add_update c, ev, k0, 10, 11, 8, 9
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add_update c, od, k0, 11, 8, 9, 10
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add_update c, ev, k1, 8, 9, 10, 11
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add_update p, od, k1, 9, 10, 11, 8
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add_update p, ev, k1, 10, 11, 8, 9
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add_update p, od, k1, 11, 8, 9, 10
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add_update p, ev, k1, 8, 9, 10, 11
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add_update p, od, k2, 9, 10, 11, 8
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add_update m, ev, k2, 10, 11, 8, 9
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add_update m, od, k2, 11, 8, 9, 10
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add_update m, ev, k2, 8, 9, 10, 11
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add_update m, od, k2, 9, 10, 11, 8
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add_update m, ev, k3, 10, 11, 8, 9
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add_update p, od, k3, 11, 8, 9, 10
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add_only p, ev, k3, 9
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add_only p, od, k3, 10
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add_only p, ev, k3, 11
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add_only p, od
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/* update state */
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add dgbv.2s, dgbv.2s, dg1v.2s
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add dgav.4s, dgav.4s, dg0v.4s
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cbnz w2, 0b
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/*
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* Final block: add padding and total bit count.
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* Skip if the input size was not a round multiple of the block size,
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* the padding is handled by the C code in that case.
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*/
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cbz x4, 3f
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ldr x4, [x0, #:lo12:sha1_ce_offsetof_count]
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movi v9.2d, #0
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mov x8, #0x80000000
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movi v10.2d, #0
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ror x7, x4, #29 // ror(lsl(x4, 3), 32)
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fmov d8, x8
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mov x4, #0
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mov v11.d[0], xzr
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mov v11.d[1], x7
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b 1b
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/* store new state */
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3: st1 {dgav.4s}, [x0]
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str dgb, [x0, #16]
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ret
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ENDPROC(sha1_ce_transform)
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