mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 16:09:57 +07:00
a7419ff8b7
MAC is connected to a PHY in RGMII mode. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
384 lines
9.4 KiB
Plaintext
384 lines
9.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
*/
|
|
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
|
|
|
/ {
|
|
soc {
|
|
pinctrl: pin-controller@50002000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-pinctrl";
|
|
ranges = <0 0x50002000 0xa400>;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&exti 0x60 0xff>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@50002000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc GPIOA>;
|
|
st,bank-name = "GPIOA";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 0 16>;
|
|
};
|
|
|
|
gpiob: gpio@50003000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc GPIOB>;
|
|
st,bank-name = "GPIOB";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 16 16>;
|
|
};
|
|
|
|
gpioc: gpio@50004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc GPIOC>;
|
|
st,bank-name = "GPIOC";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 32 16>;
|
|
};
|
|
|
|
gpiod: gpio@50005000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x3000 0x400>;
|
|
clocks = <&rcc GPIOD>;
|
|
st,bank-name = "GPIOD";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 48 16>;
|
|
};
|
|
|
|
gpioe: gpio@50006000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x4000 0x400>;
|
|
clocks = <&rcc GPIOE>;
|
|
st,bank-name = "GPIOE";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 64 16>;
|
|
};
|
|
|
|
gpiof: gpio@50007000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x5000 0x400>;
|
|
clocks = <&rcc GPIOF>;
|
|
st,bank-name = "GPIOF";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 80 16>;
|
|
};
|
|
|
|
gpiog: gpio@50008000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x6000 0x400>;
|
|
clocks = <&rcc GPIOG>;
|
|
st,bank-name = "GPIOG";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 96 16>;
|
|
};
|
|
|
|
gpioh: gpio@50009000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x7000 0x400>;
|
|
clocks = <&rcc GPIOH>;
|
|
st,bank-name = "GPIOH";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 112 16>;
|
|
};
|
|
|
|
gpioi: gpio@5000a000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x8000 0x400>;
|
|
clocks = <&rcc GPIOI>;
|
|
st,bank-name = "GPIOI";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 128 16>;
|
|
};
|
|
|
|
gpioj: gpio@5000b000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x9000 0x400>;
|
|
clocks = <&rcc GPIOJ>;
|
|
st,bank-name = "GPIOJ";
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 144 16>;
|
|
};
|
|
|
|
gpiok: gpio@5000c000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xa000 0x400>;
|
|
clocks = <&rcc GPIOK>;
|
|
st,bank-name = "GPIOK";
|
|
ngpios = <8>;
|
|
gpio-ranges = <&pinctrl 0 160 8>;
|
|
};
|
|
|
|
cec_pins_a: cec-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 15, AF4)>;
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
ethernet0_rgmii_pins_a: rgmii-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
|
|
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
|
|
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
|
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
|
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
|
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
|
|
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
|
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
|
|
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
|
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
|
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
|
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
|
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
|
|
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
|
|
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
|
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
|
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
|
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
|
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
|
|
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
|
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
|
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
|
|
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
|
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
|
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
|
|
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
|
|
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
|
|
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
|
|
};
|
|
};
|
|
|
|
i2c1_pins_a: i2c1-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
|
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
i2c2_pins_a: i2c2-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
|
|
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
i2c5_pins_a: i2c5-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
|
|
<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
m_can1_pins_a: m-can1-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
|
slew-rate = <1>;
|
|
drive-push-pull;
|
|
bias-disable;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pwm2_pins_a: pwm2-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm8_pins_a: pwm8-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
pwm12_pins_a: pwm12-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
|
|
bias-pull-down;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
qspi_clk_pins_a: qspi-clk-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
|
|
qspi_bk1_pins_a: qspi-bk1-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
|
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
|
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
|
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
|
bias-pull-up;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
|
|
qspi_bk2_pins_a: qspi-bk2-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
|
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
|
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
|
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
|
bias-pull-up;
|
|
drive-push-pull;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
|
|
uart4_pins_a: uart4-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pinctrl_z: pin-controller-z@54004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-z-pinctrl";
|
|
ranges = <0 0x54004000 0x400>;
|
|
pins-are-numbered;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&exti 0x60 0xff>;
|
|
|
|
gpioz: gpio@54004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0 0x400>;
|
|
clocks = <&rcc GPIOZ>;
|
|
st,bank-name = "GPIOZ";
|
|
st,bank-ioport = <11>;
|
|
ngpios = <8>;
|
|
gpio-ranges = <&pinctrl_z 0 400 8>;
|
|
};
|
|
|
|
i2c4_pins_a: i2c4-0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
|
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
spi1_pins_a: spi1-0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
|
|
<STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <1>;
|
|
};
|
|
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|