mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 13:36:44 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
162 lines
3.4 KiB
C
162 lines
3.4 KiB
C
/*
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* linux/arch/arm/common/icst307.c
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Support functions for calculating clocks/divisors for the ICST307
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* clock generators. See http://www.icst.com/ for more information
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* on these devices.
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*
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* This is an almost identical implementation to the ICST525 clock generator.
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* The s2div and idx2s files are different
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <asm/hardware/icst307.h>
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/*
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* Divisors for each OD setting.
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*/
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static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
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unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco)
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{
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return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
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}
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EXPORT_SYMBOL(icst307_khz);
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/*
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* Ascending divisor S values.
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*/
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static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
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struct icst307_vco
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icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq)
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{
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struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
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unsigned long f;
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unsigned int i = 0, rd, best = (unsigned int)-1;
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/*
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* First, find the PLL output divisor such
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* that the PLL output is within spec.
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*/
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do {
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f = freq * s2div[idx2s[i]];
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/*
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* f must be between 6MHz and 200MHz (3.3 or 5V)
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*/
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if (f > 6000 && f <= p->vco_max)
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break;
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} while (i < ARRAY_SIZE(idx2s));
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if (i > ARRAY_SIZE(idx2s))
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return vco;
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vco.s = idx2s[i];
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/*
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* Now find the closest divisor combination
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* which gives a PLL output of 'f'.
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*/
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for (rd = p->rd_min; rd <= p->rd_max; rd++) {
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unsigned long fref_div, f_pll;
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unsigned int vd;
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int f_diff;
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fref_div = (2 * p->ref) / rd;
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vd = (f + fref_div / 2) / fref_div;
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if (vd < p->vd_min || vd > p->vd_max)
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continue;
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f_pll = fref_div * vd;
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f_diff = f_pll - f;
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if (f_diff < 0)
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f_diff = -f_diff;
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if ((unsigned)f_diff < best) {
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vco.v = vd - 8;
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vco.r = rd - 2;
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if (f_diff == 0)
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break;
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best = f_diff;
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}
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}
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return vco;
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}
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EXPORT_SYMBOL(icst307_khz_to_vco);
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struct icst307_vco
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icst307_ps_to_vco(const struct icst307_params *p, unsigned long period)
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{
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struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
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unsigned long f, ps;
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unsigned int i = 0, rd, best = (unsigned int)-1;
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ps = 1000000000UL / p->vco_max;
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/*
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* First, find the PLL output divisor such
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* that the PLL output is within spec.
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*/
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do {
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f = period / s2div[idx2s[i]];
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/*
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* f must be between 6MHz and 200MHz (3.3 or 5V)
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*/
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if (f >= ps && f < 1000000000UL / 6000 + 1)
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break;
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} while (i < ARRAY_SIZE(idx2s));
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if (i > ARRAY_SIZE(idx2s))
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return vco;
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vco.s = idx2s[i];
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ps = 500000000UL / p->ref;
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/*
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* Now find the closest divisor combination
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* which gives a PLL output of 'f'.
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*/
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for (rd = p->rd_min; rd <= p->rd_max; rd++) {
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unsigned long f_in_div, f_pll;
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unsigned int vd;
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int f_diff;
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f_in_div = ps * rd;
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vd = (f_in_div + f / 2) / f;
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if (vd < p->vd_min || vd > p->vd_max)
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continue;
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f_pll = (f_in_div + vd / 2) / vd;
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f_diff = f_pll - f;
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if (f_diff < 0)
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f_diff = -f_diff;
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if ((unsigned)f_diff < best) {
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vco.v = vd - 8;
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vco.r = rd - 2;
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if (f_diff == 0)
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break;
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best = f_diff;
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}
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}
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return vco;
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}
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EXPORT_SYMBOL(icst307_ps_to_vco);
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