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bd2c6636cc
Several versions of DW DMAC have multi block transfers hardware support. Hardware support of multi block transfers is disabled by default if we use DT to configure DMAC and software emulation of multi block transfers used instead. Add multi-block property, so it is possible to enable hardware multi block transfers (if present) via DT. Switch from per device is_nollp variable to multi_block array to be able enable/disable multi block transfers separately per channel. Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
71 lines
2.2 KiB
Plaintext
71 lines
2.2 KiB
Plaintext
* Synopsys Designware DMA Controller
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Required properties:
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- compatible: "snps,dma-spear1340"
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- reg: Address range of the DMAC registers
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- interrupt: Should contain the DMAC interrupt number
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- dma-channels: Number of channels supported by hardware
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- dma-requests: Number of DMA request lines supported, up to 16
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- dma-masters: Number of AHB masters supported by the controller
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- #dma-cells: must be <3>
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- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
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1: descending
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- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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increase from chan n->0
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- block_size: Maximum block size supported by the controller
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- data-width: Maximum data width supported by hardware per AHB master
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(in bytes, power of 2)
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Deprecated properties:
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- data_width: Maximum data width supported by hardware per AHB master
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(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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Optional properties:
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- is_private: The device channels should be marked as private and not for by the
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general purpose DMA channel allocator. False if not passed.
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- multi-block: Multi block transfers supported by hardware. Array property with
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one cell per channel. 0: not supported, 1 (default): supported.
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Example:
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dmahost: dma@fc000000 {
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compatible = "snps,dma-spear1340";
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reg = <0xfc000000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <12>;
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dma-channels = <8>;
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dma-requests = <16>;
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dma-masters = <2>;
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#dma-cells = <3>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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data-width = <8 8>;
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};
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DMA clients connected to the Designware DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each channel.
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The four cells in order are:
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1. A phandle pointing to the DMA controller
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2. The DMA request line number
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3. Memory master for transfers on allocated channel
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4. Peripheral master for transfers on allocated channel
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Example:
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serial@e0000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xe0000000 0x1000>;
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interrupts = <0 35 0x4>;
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status = "disabled";
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dmas = <&dmahost 12 0 1>,
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<&dmahost 13 0 1 0>;
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dma-names = "rx", "rx";
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};
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