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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
464 lines
14 KiB
C
464 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/net/ethernet/rocker/rocker_hw.h - Rocker switch device driver
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* Copyright (c) 2014-2016 Jiri Pirko <jiri@mellanox.com>
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* Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
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*/
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#ifndef _ROCKER_HW_H
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#define _ROCKER_HW_H
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#include <linux/types.h>
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/* Return codes */
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enum {
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ROCKER_OK = 0,
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ROCKER_ENOENT = 2,
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ROCKER_ENXIO = 6,
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ROCKER_ENOMEM = 12,
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ROCKER_EEXIST = 17,
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ROCKER_EINVAL = 22,
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ROCKER_EMSGSIZE = 90,
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ROCKER_ENOTSUP = 95,
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ROCKER_ENOBUFS = 105,
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};
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#define ROCKER_FP_PORTS_MAX 62
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#define PCI_VENDOR_ID_REDHAT 0x1b36
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#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
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#define ROCKER_PCI_BAR0_SIZE 0x2000
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/* MSI-X vectors */
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enum {
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ROCKER_MSIX_VEC_CMD,
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ROCKER_MSIX_VEC_EVENT,
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ROCKER_MSIX_VEC_TEST,
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ROCKER_MSIX_VEC_RESERVED0,
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__ROCKER_MSIX_VEC_TX,
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__ROCKER_MSIX_VEC_RX,
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#define ROCKER_MSIX_VEC_TX(port) \
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(__ROCKER_MSIX_VEC_TX + ((port) * 2))
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#define ROCKER_MSIX_VEC_RX(port) \
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(__ROCKER_MSIX_VEC_RX + ((port) * 2))
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#define ROCKER_MSIX_VEC_COUNT(portcnt) \
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(ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1)
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};
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/* Rocker bogus registers */
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#define ROCKER_BOGUS_REG0 0x0000
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#define ROCKER_BOGUS_REG1 0x0004
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#define ROCKER_BOGUS_REG2 0x0008
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#define ROCKER_BOGUS_REG3 0x000c
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/* Rocker test registers */
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#define ROCKER_TEST_REG 0x0010
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#define ROCKER_TEST_REG64 0x0018 /* 8-byte */
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#define ROCKER_TEST_IRQ 0x0020
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#define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */
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#define ROCKER_TEST_DMA_SIZE 0x0030
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#define ROCKER_TEST_DMA_CTRL 0x0034
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/* Rocker test register ctrl */
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#define ROCKER_TEST_DMA_CTRL_CLEAR BIT(0)
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#define ROCKER_TEST_DMA_CTRL_FILL BIT(1)
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#define ROCKER_TEST_DMA_CTRL_INVERT BIT(2)
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/* Rocker DMA ring register offsets */
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#define ROCKER_DMA_DESC_ADDR(x) (0x1000 + (x) * 32) /* 8-byte */
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#define ROCKER_DMA_DESC_SIZE(x) (0x1008 + (x) * 32)
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#define ROCKER_DMA_DESC_HEAD(x) (0x100c + (x) * 32)
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#define ROCKER_DMA_DESC_TAIL(x) (0x1010 + (x) * 32)
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#define ROCKER_DMA_DESC_CTRL(x) (0x1014 + (x) * 32)
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#define ROCKER_DMA_DESC_CREDITS(x) (0x1018 + (x) * 32)
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#define ROCKER_DMA_DESC_RES1(x) (0x101c + (x) * 32)
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/* Rocker dma ctrl register bits */
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#define ROCKER_DMA_DESC_CTRL_RESET BIT(0)
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/* Rocker DMA ring types */
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enum rocker_dma_type {
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ROCKER_DMA_CMD,
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ROCKER_DMA_EVENT,
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__ROCKER_DMA_TX,
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__ROCKER_DMA_RX,
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#define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2)
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#define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2)
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};
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/* Rocker DMA ring size limits and default sizes */
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#define ROCKER_DMA_SIZE_MIN 2ul
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#define ROCKER_DMA_SIZE_MAX 65536ul
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#define ROCKER_DMA_CMD_DEFAULT_SIZE 32ul
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#define ROCKER_DMA_EVENT_DEFAULT_SIZE 32ul
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#define ROCKER_DMA_TX_DEFAULT_SIZE 64ul
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#define ROCKER_DMA_TX_DESC_SIZE 256
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#define ROCKER_DMA_RX_DEFAULT_SIZE 64ul
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#define ROCKER_DMA_RX_DESC_SIZE 256
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/* Rocker DMA descriptor struct */
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struct rocker_desc {
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u64 buf_addr;
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u64 cookie;
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u16 buf_size;
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u16 tlv_size;
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u16 resv[5];
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u16 comp_err;
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};
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#define ROCKER_DMA_DESC_COMP_ERR_GEN BIT(15)
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/* Rocker DMA TLV struct */
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struct rocker_tlv {
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u32 type;
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u16 len;
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};
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/* TLVs */
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enum {
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ROCKER_TLV_CMD_UNSPEC,
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ROCKER_TLV_CMD_TYPE, /* u16 */
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ROCKER_TLV_CMD_INFO, /* nest */
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__ROCKER_TLV_CMD_MAX,
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ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
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};
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enum {
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ROCKER_TLV_CMD_TYPE_UNSPEC,
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ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
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ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,
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ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS,
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ROCKER_TLV_CMD_TYPE_GET_PORT_STATS,
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__ROCKER_TLV_CMD_TYPE_MAX,
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ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
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};
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enum {
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ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
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ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */
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ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */
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ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */
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ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME, /* binary */
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ROCKER_TLV_CMD_PORT_SETTINGS_MTU, /* u16 */
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__ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
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ROCKER_TLV_CMD_PORT_SETTINGS_MAX =
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__ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
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};
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enum {
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ROCKER_TLV_CMD_PORT_STATS_UNSPEC,
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ROCKER_TLV_CMD_PORT_STATS_PPORT, /* u32 */
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ROCKER_TLV_CMD_PORT_STATS_RX_PKTS, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_RX_BYTES, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_TX_PKTS, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_TX_BYTES, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED, /* u64 */
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ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS, /* u64 */
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__ROCKER_TLV_CMD_PORT_STATS_MAX,
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ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1,
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};
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enum rocker_port_mode {
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ROCKER_PORT_MODE_OF_DPA,
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};
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enum {
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ROCKER_TLV_EVENT_UNSPEC,
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ROCKER_TLV_EVENT_TYPE, /* u16 */
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ROCKER_TLV_EVENT_INFO, /* nest */
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__ROCKER_TLV_EVENT_MAX,
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ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
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};
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enum {
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ROCKER_TLV_EVENT_TYPE_UNSPEC,
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ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
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ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,
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__ROCKER_TLV_EVENT_TYPE_MAX,
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ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
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};
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enum {
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ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
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ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */
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ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */
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__ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
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ROCKER_TLV_EVENT_LINK_CHANGED_MAX =
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__ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
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};
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enum {
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ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
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ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */
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ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */
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ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */
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__ROCKER_TLV_EVENT_MAC_VLAN_MAX,
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ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
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};
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enum {
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ROCKER_TLV_RX_UNSPEC,
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ROCKER_TLV_RX_FLAGS, /* u16, see ROCKER_RX_FLAGS_ */
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ROCKER_TLV_RX_CSUM, /* u16 */
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ROCKER_TLV_RX_FRAG_ADDR, /* u64 */
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ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */
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ROCKER_TLV_RX_FRAG_LEN, /* u16 */
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__ROCKER_TLV_RX_MAX,
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ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
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};
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#define ROCKER_RX_FLAGS_IPV4 BIT(0)
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#define ROCKER_RX_FLAGS_IPV6 BIT(1)
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#define ROCKER_RX_FLAGS_CSUM_CALC BIT(2)
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#define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD BIT(3)
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#define ROCKER_RX_FLAGS_IP_FRAG BIT(4)
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#define ROCKER_RX_FLAGS_TCP BIT(5)
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#define ROCKER_RX_FLAGS_UDP BIT(6)
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#define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD BIT(7)
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#define ROCKER_RX_FLAGS_FWD_OFFLOAD BIT(8)
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enum {
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ROCKER_TLV_TX_UNSPEC,
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ROCKER_TLV_TX_OFFLOAD, /* u8, see ROCKER_TX_OFFLOAD_ */
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ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */
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ROCKER_TLV_TX_TSO_MSS, /* u16 */
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ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */
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ROCKER_TLV_TX_FRAGS, /* array */
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__ROCKER_TLV_TX_MAX,
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ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
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};
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#define ROCKER_TX_OFFLOAD_NONE 0
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#define ROCKER_TX_OFFLOAD_IP_CSUM 1
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#define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2
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#define ROCKER_TX_OFFLOAD_L3_CSUM 3
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#define ROCKER_TX_OFFLOAD_TSO 4
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#define ROCKER_TX_FRAGS_MAX 16
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enum {
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ROCKER_TLV_TX_FRAG_UNSPEC,
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ROCKER_TLV_TX_FRAG, /* nest */
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__ROCKER_TLV_TX_FRAG_MAX,
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ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
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};
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enum {
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ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
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ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */
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ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */
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__ROCKER_TLV_TX_FRAG_ATTR_MAX,
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ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
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};
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/* cmd info nested for OF-DPA msgs */
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enum {
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ROCKER_TLV_OF_DPA_UNSPEC,
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ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */
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ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */
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ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */
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ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */
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ROCKER_TLV_OF_DPA_COOKIE, /* u64 */
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ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */
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ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */
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ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */
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ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */
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ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */
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ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */
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ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */
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ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */
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ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */
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ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */
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ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */
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ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */
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ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */
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ROCKER_TLV_OF_DPA_DST_MAC, /* binary */
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ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */
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ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */
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ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */
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ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */
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ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */
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ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */
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ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */
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ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */
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ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */
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ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */
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ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */
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ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */
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ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */
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__ROCKER_TLV_OF_DPA_MAX,
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ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
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};
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/* OF-DPA table IDs */
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enum rocker_of_dpa_table_id {
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ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
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ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
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ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
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ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
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ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
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ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
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ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
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};
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/* OF-DPA flow stats */
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enum {
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ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
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ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */
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ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */
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ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */
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|
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__ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
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ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
|
|
};
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|
|
|
/* OF-DPA group types */
|
|
enum rocker_of_dpa_group_type {
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ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
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ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
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|
ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
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ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
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|
ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
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ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
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|
ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
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|
ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
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|
ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
|
|
};
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|
|
|
/* OF-DPA group L2 overlay types */
|
|
enum rocker_of_dpa_overlay_type {
|
|
ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
|
|
ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
|
|
ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
|
|
ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
|
|
};
|
|
|
|
/* OF-DPA group ID encoding */
|
|
#define ROCKER_GROUP_TYPE_SHIFT 28
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|
#define ROCKER_GROUP_TYPE_MASK 0xf0000000
|
|
#define ROCKER_GROUP_VLAN_SHIFT 16
|
|
#define ROCKER_GROUP_VLAN_MASK 0x0fff0000
|
|
#define ROCKER_GROUP_PORT_SHIFT 0
|
|
#define ROCKER_GROUP_PORT_MASK 0x0000ffff
|
|
#define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
|
|
#define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
|
|
#define ROCKER_GROUP_SUBTYPE_SHIFT 10
|
|
#define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
|
|
#define ROCKER_GROUP_INDEX_SHIFT 0
|
|
#define ROCKER_GROUP_INDEX_MASK 0x0000ffff
|
|
#define ROCKER_GROUP_INDEX_LONG_SHIFT 0
|
|
#define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff
|
|
|
|
#define ROCKER_GROUP_TYPE_GET(group_id) \
|
|
(((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
|
|
#define ROCKER_GROUP_TYPE_SET(type) \
|
|
(((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
|
|
#define ROCKER_GROUP_VLAN_GET(group_id) \
|
|
(((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
|
|
#define ROCKER_GROUP_VLAN_SET(vlan_id) \
|
|
(((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK)
|
|
#define ROCKER_GROUP_PORT_GET(group_id) \
|
|
(((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
|
|
#define ROCKER_GROUP_PORT_SET(port) \
|
|
(((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
|
|
#define ROCKER_GROUP_INDEX_GET(group_id) \
|
|
(((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
|
|
#define ROCKER_GROUP_INDEX_SET(index) \
|
|
(((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
|
|
#define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
|
|
(((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
|
|
ROCKER_GROUP_INDEX_LONG_SHIFT)
|
|
#define ROCKER_GROUP_INDEX_LONG_SET(index) \
|
|
(((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
|
|
ROCKER_GROUP_INDEX_LONG_MASK)
|
|
|
|
#define ROCKER_GROUP_NONE 0
|
|
#define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
|
|
(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\
|
|
ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port))
|
|
#define ROCKER_GROUP_L2_REWRITE(index) \
|
|
(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\
|
|
ROCKER_GROUP_INDEX_LONG_SET(index))
|
|
#define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
|
|
(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\
|
|
ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
|
|
#define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
|
|
(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\
|
|
ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
|
|
#define ROCKER_GROUP_L3_UNICAST(index) \
|
|
(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\
|
|
ROCKER_GROUP_INDEX_LONG_SET(index))
|
|
|
|
/* Rocker general purpose registers */
|
|
#define ROCKER_CONTROL 0x0300
|
|
#define ROCKER_PORT_PHYS_COUNT 0x0304
|
|
#define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */
|
|
#define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */
|
|
#define ROCKER_SWITCH_ID 0x0320 /* 8-byte */
|
|
|
|
/* Rocker control bits */
|
|
#define ROCKER_CONTROL_RESET BIT(0)
|
|
|
|
#endif
|