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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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731da21b7b
Avoids overflows on DCE2.x devices. Also clarify the calculation on other asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
301 lines
11 KiB
C
301 lines
11 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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* Rafał Miłecki
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*/
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "evergreend.h"
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#include "atom.h"
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/*
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* update the N and CTS parameters for a given pixel clock rate
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*/
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static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
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WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
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WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
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WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
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WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
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WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
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}
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static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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struct cea_sad *sads;
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int i, sad_count;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder)
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radeon_connector = to_radeon_connector(connector);
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
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if (sad_count < 0) {
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DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
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return;
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}
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BUG_ON(!sads);
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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value = MAX_CHANNELS(sad->channels) |
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DESCRIPTOR_BYTE_2(sad->byte2) |
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SUPPORTED_FREQUENCIES(sad->freq);
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
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break;
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}
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}
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WREG32(eld_reg_to_type[i][0], value);
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}
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kfree(sads);
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}
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/*
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* build a HDMI Video Info Frame
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*/
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static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
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void *buffer, size_t size)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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uint8_t *frame = buffer + 3;
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/* Our header values (type, version, length) should be alright, Intel
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* is using the same. Checksum function also seems to be OK, it works
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* fine for audio infoframe. However calculated value is always lower
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* by 2 in comparison to fglrx. It breaks displaying anything in case
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* of TVs that strictly check the checksum. Hack it manually here to
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* workaround this issue. */
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frame[0x0] += 2;
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WREG32(AFMT_AVI_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(AFMT_AVI_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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WREG32(AFMT_AVI_INFO2 + offset,
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frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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WREG32(AFMT_AVI_INFO3 + offset,
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frame[0xC] | (frame[0xD] << 8));
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}
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static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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u32 base_rate = 24000;
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if (!dig || !dig->afmt)
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return;
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/* XXX two dtos; generally use dto0 for hdmi */
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
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}
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/*
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* update the info frames with the data from the current display mode
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*/
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void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
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struct hdmi_avi_infoframe frame;
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uint32_t offset;
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ssize_t err;
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/* Silent, r600_hdmi_enable will raise WARN for us */
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if (!dig->afmt->enabled)
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return;
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offset = dig->afmt->offset;
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evergreen_audio_set_dto(encoder, mode->clock);
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WREG32(HDMI_VBI_PACKET_CONTROL + offset,
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HDMI_NULL_SEND); /* send null packets when required */
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WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
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WREG32(HDMI_VBI_PACKET_CONTROL + offset,
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HDMI_NULL_SEND | /* send null packets when required */
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HDMI_GC_SEND | /* send general control packets */
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HDMI_GC_CONT); /* send general control packets every frame */
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WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
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HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
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WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
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AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
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WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
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HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
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WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
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WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
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HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
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HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
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WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
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AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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HDMI_ACR_SOURCE); /* select SW CTS value */
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evergreen_hdmi_update_ACR(encoder, mode->clock);
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WREG32(AFMT_60958_0 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_L(1));
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WREG32(AFMT_60958_1 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_R(2));
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WREG32(AFMT_60958_2 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
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AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
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AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
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AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
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AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
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AFMT_60958_CS_CHANNEL_NUMBER_7(8));
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/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
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WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
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AFMT_AUDIO_CHANNEL_ENABLE(0xff));
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/* fglrx sets 0x40 in 0x5f80 here */
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evergreen_hdmi_write_sad_regs(encoder);
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err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
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if (err < 0) {
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DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
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return;
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}
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err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
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if (err < 0) {
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DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
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return;
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}
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evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
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WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
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HDMI_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
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WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
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HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
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~HDMI_AVI_INFO_LINE_MASK);
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WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
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AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
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/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
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WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
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WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
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WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
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WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
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}
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void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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/* Silent, r600_hdmi_enable will raise WARN for us */
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if (enable && dig->afmt->enabled)
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return;
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if (!enable && !dig->afmt->enabled)
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return;
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dig->afmt->enabled = enable;
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DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
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enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
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}
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