Vijay Purushothaman 9473c8f485 drm/i915: Set aux clk to 100MHz for Valleyview ... Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview. This enables the aux transactions in Valleyview. Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2012-09-28 16:42:52 +02:00
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drm	drm/i915: Set aux clk to 100MHz for Valleyview	2012-09-28 16:42:52 +02:00
stub
vga	vga_switcheroo: Don't require handler init callback	2012-08-17 17:34:41 -04:00
Makefile