mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 13:36:45 +07:00
945f2672cc
Add support for reading out the cdclk frequency from the hardware on CNL. Very similar to BXT, with a few new twists and turns: * the PLL is now called CDCLK PLL, not DE PLL * reference clock can be 24 MHz in addition to the 19.2 MHz BXT had * the ratio now lives in the PLL enable register * Only 1x and 2x CD2X dividers are supported v2: Deal with PLL lock bit the same way as BXT/SKL do now v3: DSSM refclk indicator is bit 31 not 24 (Ander) v4: Rebased by Rodrigo after Ville's cdclk rework. v5: Set cdclk to the ref clock as previous platforms. (Imre) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-1-git-send-email-rodrigo.vivi@intel.com |
||
|---|---|---|
| .. | ||
| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||