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7903782460
Thunderbolt hotplug ports that were occupied before system sleep resume
with their downstream link in "off" state. Only after the Thunderbolt
controller has reestablished the PCIe tunnels does the link go up.
As a result, a spurious Presence Detect Changed and/or Data Link Layer
State Changed event occurs.
The events are not immediately acted upon because tunnel reestablishment
happens in the ->resume_noirq phase, when interrupts are still disabled.
Also, notification of events may initially be disabled in the Slot
Control register when coming out of system sleep and is reenabled in the
->resume_noirq phase through:
pci_pm_resume_noirq()
pci_pm_default_resume_early()
pci_restore_state()
pci_restore_pcie_state()
It is not guaranteed that the events are acted upon at all: PCIe r4.0,
sec 6.7.3.4 says that "a port may optionally send an MSI when there are
hot-plug events that occur while interrupt generation is disabled, and
interrupt generation is subsequently enabled." Note the "optionally".
If an MSI is sent, pciehp will gratuitously turn the slot off and back
on once the ->resume_early phase has commenced.
If an MSI is not sent, the extant, unacknowledged events in the Slot
Status register will prevent future notification of presence or link
changes.
Commit 13c65840fe ("PCI: pciehp: Clear Presence Detect and Data Link
Layer Status Changed on resume") fixed the latter by clearing the events
in the ->resume phase. Move this to the ->resume_noirq phase to also
fix the gratuitous disable/enablement of the slot.
The commit further restored the Slot Control register in the ->resume
phase, but that's dispensable because as shown above it's already been
done in the ->resume_noirq phase.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Purpose: PCI Express Port Bus Driver's Internal Data Structures
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef _PORTDRV_H_
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#define _PORTDRV_H_
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#include <linux/compiler.h>
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/* Service Type */
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#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
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#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
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#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
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#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
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#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
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#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
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#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
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#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
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#define PCIE_PORT_DEVICE_MAXSERVICES 4
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/* Port Type */
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#define PCIE_ANY_PORT (~0)
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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struct pci_dev *port; /* Root/Upstream/Downstream Port */
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u32 service; /* Port service this device represents */
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void *priv_data; /* Service Private Data */
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struct device device; /* Generic Device Interface */
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};
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#define to_pcie_device(d) container_of(d, struct pcie_device, device)
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static inline void set_service_data(struct pcie_device *dev, void *data)
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{
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dev->priv_data = data;
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}
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static inline void *get_service_data(struct pcie_device *dev)
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{
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return dev->priv_data;
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}
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struct pcie_port_service_driver {
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const char *name;
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int (*probe) (struct pcie_device *dev);
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void (*remove) (struct pcie_device *dev);
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int (*suspend) (struct pcie_device *dev);
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int (*resume_noirq) (struct pcie_device *dev);
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int (*resume) (struct pcie_device *dev);
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/* Device driver may resume normal operations */
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void (*error_resume)(struct pci_dev *dev);
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/* Link Reset Capability - AER service driver specific */
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pci_ers_result_t (*reset_link) (struct pci_dev *dev);
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int port_type; /* Type of the port this driver can handle */
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u32 service; /* Port service this device represents */
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struct device_driver driver;
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};
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#define to_service_driver(d) \
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container_of(d, struct pcie_port_service_driver, driver)
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int pcie_port_service_register(struct pcie_port_service_driver *new);
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void pcie_port_service_unregister(struct pcie_port_service_driver *new);
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/*
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* The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
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* be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
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* supports a maximum of 32 vectors per function.
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*/
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#define PCIE_PORT_MAX_MSI_ENTRIES 32
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#define get_descriptor_id(type, service) (((type - 4) << 8) | service)
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extern struct bus_type pcie_port_bus_type;
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int pcie_port_device_register(struct pci_dev *dev);
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#ifdef CONFIG_PM
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int pcie_port_device_suspend(struct device *dev);
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int pcie_port_device_resume_noirq(struct device *dev);
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int pcie_port_device_resume(struct device *dev);
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#endif
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void pcie_port_device_remove(struct pci_dev *dev);
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int __must_check pcie_port_bus_register(void);
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void pcie_port_bus_unregister(void);
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struct pci_dev;
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#ifdef CONFIG_PCIE_PME
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extern bool pcie_pme_msi_disabled;
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static inline void pcie_pme_disable_msi(void)
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{
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pcie_pme_msi_disabled = true;
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}
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static inline bool pcie_pme_no_msi(void)
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{
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return pcie_pme_msi_disabled;
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}
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void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
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#else /* !CONFIG_PCIE_PME */
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static inline void pcie_pme_disable_msi(void) {}
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static inline bool pcie_pme_no_msi(void) { return false; }
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static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
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#endif /* !CONFIG_PCIE_PME */
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#ifdef CONFIG_ACPI_APEI
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int pcie_aer_get_firmware_first(struct pci_dev *pci_dev);
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#else
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static inline int pcie_aer_get_firmware_first(struct pci_dev *pci_dev)
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{
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if (pci_dev->__aer_firmware_first_valid)
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return pci_dev->__aer_firmware_first;
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return 0;
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}
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#endif
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#ifdef CONFIG_PCIEAER
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irqreturn_t aer_irq(int irq, void *context);
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#endif
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struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev,
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u32 service);
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struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
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#endif /* _PORTDRV_H_ */
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