mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 11:35:07 +07:00
3a936bc286
On the Amlogic GXL & GXM SoCs, a bug occurs on the primary plane when alpha is used where the alpha is not aligned with the pixel content. The workaround Amlogic implemented is to reset the OSD1 plane hardware block each time the plane is (re)enabled, solving the issue. In the reset, we still need to save the content of 2 registers which depends on the status of the plane, in addition to reload the scaler conversion matrix at the same time. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com> [narmstrong: fixed typo in commit log] Link: https://patchwork.freedesktop.org/patch/msgid/20181128100734.6536-1-narmstrong@baylibre.com
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/*
|
|
* Copyright (C) 2016 BayLibre, SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
/* Video Input Unit */
|
|
|
|
#ifndef __MESON_VIU_H
|
|
#define __MESON_VIU_H
|
|
|
|
/* OSDx_BLKx_CFG */
|
|
#define OSD_CANVAS_SEL 16
|
|
|
|
#define OSD_ENDIANNESS_LE BIT(15)
|
|
#define OSD_ENDIANNESS_BE (0)
|
|
|
|
#define OSD_BLK_MODE_422 (0x03 << 8)
|
|
#define OSD_BLK_MODE_16 (0x04 << 8)
|
|
#define OSD_BLK_MODE_32 (0x05 << 8)
|
|
#define OSD_BLK_MODE_24 (0x07 << 8)
|
|
|
|
#define OSD_OUTPUT_COLOR_RGB BIT(7)
|
|
#define OSD_OUTPUT_COLOR_YUV (0)
|
|
|
|
#define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
|
|
#define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
|
|
#define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
|
|
#define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
|
|
|
|
#define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
|
|
|
|
#define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
|
|
#define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
|
|
|
|
#define OSD_INTERLACE_ENABLED BIT(1)
|
|
#define OSD_INTERLACE_ODD BIT(0)
|
|
#define OSD_INTERLACE_EVEN (0)
|
|
|
|
/* OSDx_CTRL_STAT */
|
|
#define OSD_ENABLE BIT(21)
|
|
#define OSD_BLK0_ENABLE BIT(0)
|
|
|
|
#define OSD_GLOBAL_ALPHA_SHIFT 12
|
|
|
|
/* OSDx_CTRL_STAT2 */
|
|
#define OSD_REPLACE_EN BIT(14)
|
|
#define OSD_REPLACE_SHIFT 6
|
|
|
|
void meson_viu_osd1_reset(struct meson_drm *priv);
|
|
void meson_viu_init(struct meson_drm *priv);
|
|
|
|
#endif /* __MESON_VIU_H */
|