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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 94 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141334.043630402@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
89 lines
3.2 KiB
C
89 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Cache flush operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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#include <linux/mm_types.h>
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/* Cache flushing:
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*
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* - flush_cache_all() flushes entire cache
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* - flush_cache_mm(mm) flushes the specified mm context's cache lines
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* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
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* - flush_cache_range(vma, start, end) flushes a range of pages
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* - flush_icache_range(start, end) flush a range of instructions
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* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
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* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
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*
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* Need to doublecheck which one is really needed for ptrace stuff to work.
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*/
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#define LINESIZE 32
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#define LINEBITS 5
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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/*
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* Flush Dcache range through current map.
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*/
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extern void flush_dcache_range(unsigned long start, unsigned long end);
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/*
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* Flush Icache range through current map.
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*/
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extern void flush_icache_range(unsigned long start, unsigned long end);
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/*
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* Memory-management related flushes are there to ensure in non-physically
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* indexed cache schemes that stale lines belonging to a given ASID aren't
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* in the cache to confuse things. The prototype Hexagon Virtual Machine
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* only uses a single ASID for all user-mode maps, which should
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* mean that they aren't necessary. A brute-force, flush-everything
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* implementation, with the name xxxxx_hexagon() is present in
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* arch/hexagon/mm/cache.c, but let's not wire it up until we know
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* it is needed.
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*/
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extern void flush_cache_all_hexagon(void);
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/*
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* This may or may not ever have to be non-null, depending on the
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* virtual machine MMU. For a native kernel, it's definitiely a no-op
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*
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* This is also the place where deferred cache coherency stuff seems
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* to happen, classically... but instead we do it like ia64 and
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* clean the cache when the PTE is set.
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*
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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/* generic_ptrace_pokedata doesn't wind up here, does it? */
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}
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, void *src, int len);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
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extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
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#endif
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