mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6f2b6422d4
Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If EDAC is enabled, it will prevent the platform from going into suspend. The reason is that the IRQ vectors for OCRAM reside on DDR and in Suspend-to-RAM mode we're executing out of OCRAM. If an ECC error occurs, we can't handle it so it was decided to make them mutually exclusive. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: dinh.linux@gmail.com Cc: dougthompson@xmission.com Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: tthayer@opensource.altera.com Link: http://lkml.kernel.org/r/1433512155-9906-1-git-send-email-dinguyen@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
514 lines
14 KiB
C
514 lines
14 KiB
C
/*
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* Copyright Altera Corporation (C) 2014-2015. All rights reserved.
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Adapted from the highbank_mc_edac driver.
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*/
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#include <linux/ctype.h>
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#include <linux/edac.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include "altera_edac.h"
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#include "edac_core.h"
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#include "edac_module.h"
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#define EDAC_MOD_STR "altera_edac"
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#define EDAC_VERSION "1"
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static const struct altr_sdram_prv_data c5_data = {
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.ecc_ctrl_offset = CV_CTLCFG_OFST,
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.ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
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.ecc_stat_offset = CV_DRAMSTS_OFST,
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.ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
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.ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
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.ecc_saddr_offset = CV_ERRADDR_OFST,
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.ecc_daddr_offset = CV_ERRADDR_OFST,
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.ecc_cecnt_offset = CV_SBECOUNT_OFST,
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.ecc_uecnt_offset = CV_DBECOUNT_OFST,
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.ecc_irq_en_offset = CV_DRAMINTR_OFST,
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.ecc_irq_en_mask = CV_DRAMINTR_INTREN,
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.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
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.ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
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.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
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.ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
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#ifdef CONFIG_EDAC_DEBUG
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.ce_ue_trgr_offset = CV_CTLCFG_OFST,
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.ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
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.ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
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#endif
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};
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static const struct altr_sdram_prv_data a10_data = {
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.ecc_ctrl_offset = A10_ECCCTRL1_OFST,
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.ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
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.ecc_stat_offset = A10_INTSTAT_OFST,
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.ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
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.ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
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.ecc_saddr_offset = A10_SERRADDR_OFST,
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.ecc_daddr_offset = A10_DERRADDR_OFST,
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.ecc_irq_en_offset = A10_ERRINTEN_OFST,
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.ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
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.ecc_irq_clr_offset = A10_INTSTAT_OFST,
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.ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
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.ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
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.ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
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#ifdef CONFIG_EDAC_DEBUG
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.ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
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.ce_set_mask = A10_DIAGINT_TSERRA_MASK,
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.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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#endif
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};
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static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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const struct altr_sdram_prv_data *priv = drvdata->data;
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u32 status, err_count = 1, err_addr;
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regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
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if (status & priv->ecc_stat_ue_mask) {
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regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
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&err_addr);
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if (priv->ecc_uecnt_offset)
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regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
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&err_count);
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panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
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err_count, err_addr);
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}
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if (status & priv->ecc_stat_ce_mask) {
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regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
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&err_addr);
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if (priv->ecc_uecnt_offset)
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regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
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&err_count);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
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err_addr >> PAGE_SHIFT,
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err_addr & ~PAGE_MASK, 0,
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0, 0, -1, mci->ctl_name, "");
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/* Clear IRQ to resume */
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regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
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priv->ecc_irq_clr_mask);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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#ifdef CONFIG_EDAC_DEBUG
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static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
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const char __user *data,
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size_t count, loff_t *ppos)
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{
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struct mem_ctl_info *mci = file->private_data;
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struct altr_sdram_mc_data *drvdata = mci->pvt_info;
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const struct altr_sdram_prv_data *priv = drvdata->data;
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u32 *ptemp;
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dma_addr_t dma_handle;
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u32 reg, read_reg;
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ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
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if (!ptemp) {
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dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
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edac_printk(KERN_ERR, EDAC_MC,
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"Inject: Buffer Allocation error\n");
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return -ENOMEM;
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}
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regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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&read_reg);
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read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
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/* Error are injected by writing a word while the SBE or DBE
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* bit in the CTLCFG register is set. Reading the word will
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* trigger the SBE or DBE error and the corresponding IRQ.
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*/
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if (count == 3) {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Double bit error\n");
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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(read_reg | priv->ue_set_mask));
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} else {
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edac_printk(KERN_ALERT, EDAC_MC,
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"Inject Single bit error\n");
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
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(read_reg | priv->ce_set_mask));
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}
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ptemp[0] = 0x5A5A5A5A;
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ptemp[1] = 0xA5A5A5A5;
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/* Clear the error injection bits */
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regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
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/* Ensure it has been written out */
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wmb();
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/*
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* To trigger the error, we need to read the data back
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* (the data was written with errors above).
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* The ACCESS_ONCE macros and printk are used to prevent the
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* the compiler optimizing these reads out.
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*/
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reg = ACCESS_ONCE(ptemp[0]);
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read_reg = ACCESS_ONCE(ptemp[1]);
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/* Force Read */
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rmb();
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edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
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reg, read_reg);
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dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
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return count;
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}
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static const struct file_operations altr_sdr_mc_debug_inject_fops = {
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.open = simple_open,
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.write = altr_sdr_mc_err_inject_write,
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.llseek = generic_file_llseek,
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};
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static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
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{
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if (mci->debugfs)
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debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
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&altr_sdr_mc_debug_inject_fops);
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}
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#else
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static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
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{}
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#endif
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/* Get total memory size from Open Firmware DTB */
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static unsigned long get_total_mem(void)
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{
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struct device_node *np = NULL;
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const unsigned int *reg, *reg_end;
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int len, sw, aw;
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unsigned long start, size, total_mem = 0;
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for_each_node_by_type(np, "memory") {
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aw = of_n_addr_cells(np);
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sw = of_n_size_cells(np);
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reg = (const unsigned int *)of_get_property(np, "reg", &len);
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reg_end = reg + (len / sizeof(u32));
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total_mem = 0;
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do {
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start = of_read_number(reg, aw);
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reg += aw;
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size = of_read_number(reg, sw);
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reg += sw;
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total_mem += size;
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} while (reg < reg_end);
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}
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edac_dbg(0, "total_mem 0x%lx\n", total_mem);
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return total_mem;
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}
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
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{ .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
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static int a10_init(struct regmap *mc_vbase)
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{
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if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
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A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error setting SB IRQ mode\n");
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return -ENODEV;
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}
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if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error setting trigger count\n");
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return -ENODEV;
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}
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return 0;
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}
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static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
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{
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void __iomem *sm_base;
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int ret = 0;
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if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
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dev_name(&pdev->dev))) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to request mem region\n");
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return -EBUSY;
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}
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sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
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if (!sm_base) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to ioremap device\n");
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ret = -ENOMEM;
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goto release;
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}
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iowrite32(mask, sm_base);
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iounmap(sm_base);
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release:
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release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
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return ret;
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}
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static int altr_sdram_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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struct altr_sdram_mc_data *drvdata;
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const struct altr_sdram_prv_data *priv;
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struct regmap *mc_vbase;
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struct dimm_info *dimm;
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u32 read_reg;
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int irq, irq2, res = 0;
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unsigned long mem_size, irqflags = 0;
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id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
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if (!id)
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return -ENODEV;
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/* Grab the register range from the sdr controller in device tree */
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mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"altr,sdr-syscon");
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if (IS_ERR(mc_vbase)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"regmap for altr,sdr-syscon lookup failed.\n");
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return -ENODEV;
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}
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/* Check specific dependencies for the module */
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priv = of_match_node(altr_sdram_ctrl_of_match,
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pdev->dev.of_node)->data;
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/* Validate the SDRAM controller has ECC enabled */
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if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
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((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No ECC/ECC disabled [0x%08X]\n", read_reg);
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return -ENODEV;
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}
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/* Grab memory size from device tree. */
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mem_size = get_total_mem();
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if (!mem_size) {
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edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
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return -ENODEV;
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}
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/* Ensure the SDRAM Interrupt is disabled */
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if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
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priv->ecc_irq_en_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error disabling SDRAM ECC IRQ\n");
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return -ENODEV;
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}
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/* Toggle to clear the SDRAM Error count */
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if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask,
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priv->ecc_cnt_rst_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No irq %d in DT\n", irq);
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return -ENODEV;
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}
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/* Arria10 has a 2nd IRQ */
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irq2 = platform_get_irq(pdev, 1);
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 1;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = 1;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct altr_sdram_mc_data));
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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drvdata = mci->pvt_info;
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drvdata->mc_vbase = mc_vbase;
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drvdata->data = priv;
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platform_set_drvdata(pdev, mci);
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to get managed device resource\n");
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res = -ENOMEM;
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goto free;
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}
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = EDAC_VERSION;
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mci->ctl_name = dev_name(&pdev->dev);
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mci->scrub_mode = SCRUB_SW_SRC;
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mci->dev_name = dev_name(&pdev->dev);
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dimm = *mci->dimms;
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dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
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dimm->grain = 8;
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dimm->dtype = DEV_X8;
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dimm->mtype = MEM_DDR3;
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dimm->edac_mode = EDAC_SECDED;
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res = edac_mc_add_mc(mci);
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if (res < 0)
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goto err;
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/* Only the Arria10 has separate IRQs */
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if (irq2 > 0) {
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/* Arria10 specific initialization */
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res = a10_init(mc_vbase);
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if (res < 0)
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goto err2;
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res = devm_request_irq(&pdev->dev, irq2,
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altr_sdram_mc_err_handler,
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IRQF_SHARED, dev_name(&pdev->dev), mci);
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if (res < 0) {
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edac_mc_printk(mci, KERN_ERR,
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"Unable to request irq %d\n", irq2);
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res = -ENODEV;
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goto err2;
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}
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res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
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if (res < 0)
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goto err2;
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irqflags = IRQF_SHARED;
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}
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res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
|
|
irqflags, dev_name(&pdev->dev), mci);
|
|
if (res < 0) {
|
|
edac_mc_printk(mci, KERN_ERR,
|
|
"Unable to request irq %d\n", irq);
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
/* Infrastructure ready - enable the IRQ */
|
|
if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
|
|
priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
|
|
edac_mc_printk(mci, KERN_ERR,
|
|
"Error enabling SDRAM ECC IRQ\n");
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
altr_sdr_mc_create_debugfs_nodes(mci);
|
|
|
|
devres_close_group(&pdev->dev, NULL);
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
edac_mc_del_mc(&pdev->dev);
|
|
err:
|
|
devres_release_group(&pdev->dev, NULL);
|
|
free:
|
|
edac_mc_free(mci);
|
|
edac_printk(KERN_ERR, EDAC_MC,
|
|
"EDAC Probe Failed; Error %d\n", res);
|
|
|
|
return res;
|
|
}
|
|
|
|
static int altr_sdram_remove(struct platform_device *pdev)
|
|
{
|
|
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
|
|
|
edac_mc_del_mc(&pdev->dev);
|
|
edac_mc_free(mci);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* If you want to suspend, need to disable EDAC by removing it
|
|
* from the device tree or defconfig.
|
|
*/
|
|
#ifdef CONFIG_PM
|
|
static int altr_sdram_prepare(struct device *dev)
|
|
{
|
|
pr_err("Suspend not allowed when EDAC is enabled.\n");
|
|
|
|
return -EPERM;
|
|
}
|
|
|
|
static const struct dev_pm_ops altr_sdram_pm_ops = {
|
|
.prepare = altr_sdram_prepare,
|
|
};
|
|
#endif
|
|
|
|
static struct platform_driver altr_sdram_edac_driver = {
|
|
.probe = altr_sdram_probe,
|
|
.remove = altr_sdram_remove,
|
|
.driver = {
|
|
.name = "altr_sdram_edac",
|
|
#ifdef CONFIG_PM
|
|
.pm = &altr_sdram_pm_ops,
|
|
#endif
|
|
.of_match_table = altr_sdram_ctrl_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(altr_sdram_edac_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Thor Thayer");
|
|
MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");
|