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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fcdc653751
RISC-V has the concept of a cpu level interrupt controller. The interface for it is split between a standardized part that is exposed as bits in the mstatus/sstatus register and the mie/mip/sie/sip CRS. But the bit to actually trigger IPIs is not standardized and just mentioned as implementable using MMIO. Add support for IPIs using MMIO using the SiFive clint layout (which is also shared by Ariane, Kendryte and the Qemu virt platform). Additionally the MMIO block also supports the time value and timer compare registers, so they are also set up using the same OF node. Support for other layouts should also be relatively easy to add in the future. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: update include guard format; fix checkpatch issues; minor commit message cleanup] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
45 lines
945 B
C
45 lines
945 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Christoph Hellwig.
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/types.h>
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#include <asm/clint.h>
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#include <asm/csr.h>
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#include <asm/timex.h>
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#include <asm/smp.h>
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/*
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* This is the layout used by the SiFive clint, which is also shared by the qemu
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* virt platform, and the Kendryte KD210 at least.
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*/
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#define CLINT_IPI_OFF 0
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#define CLINT_TIME_CMP_OFF 0x4000
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#define CLINT_TIME_VAL_OFF 0xbff8
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u32 __iomem *clint_ipi_base;
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void clint_init_boot_cpu(void)
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{
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struct device_node *np;
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void __iomem *base;
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np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
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if (!np) {
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panic("clint not found");
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return;
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}
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base = of_iomap(np, 0);
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if (!base)
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panic("could not map CLINT");
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clint_ipi_base = base + CLINT_IPI_OFF;
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riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
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riscv_time_val = base + CLINT_TIME_VAL_OFF;
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clint_clear_ipi(boot_cpu_hartid);
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}
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