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c50f9fb6c5
Now that the CCU device tree binding headers have been merged, we can use the properly named macros in the device tree, instead of raw numbers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
308 lines
7.8 KiB
Plaintext
308 lines
7.8 KiB
Plaintext
/*
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* Copyright 2015 Vishnu Patekar
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*
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* Vishnu Patekar <vishnupatekar0510@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-a83t-ccu.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/reset/sun8i-a83t-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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};
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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cpu@100 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu@101 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu@102 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu@103 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* TODO: PRCM block has a mux for this. */
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-accuracy = <50000>;
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clock-output-names = "osc24M";
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};
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/*
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* This is called "internal OSC" in some places.
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* It is an internal RC-based oscillator.
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* TODO: Its controls are in the PRCM block.
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*/
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osc16M: osc16M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "osc16M";
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};
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osc16Md512: osc16Md512_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <512>;
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clock-mult = <1>;
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clocks = <&osc16M>;
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clock-output-names = "osc16M-d512";
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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device_type = "memory";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun8i-a83t-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun8i-a83t-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-a83t-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc16Md512>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun8i-a83t-pinctrl";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x01c20800 0x400>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2",
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"PF3", "PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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spdif_tx_pin: spdif-tx-pin {
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pins = "PE18";
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function = "spdif";
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};
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB9", "PB10";
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function = "uart0";
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};
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uart0_pf_pins: uart0-pf-pins {
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pins = "PF2", "PF4";
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function = "uart0";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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watchdog@1c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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spdif: spdif@1c21000 {
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#sound-dai-cells = <0>;
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compatible = "allwinner,sun8i-a83t-spdif",
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"allwinner,sun8i-h3-spdif";
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reg = <0x01c21000 0x400>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
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resets = <&ccu RST_BUS_SPDIF>;
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clock-names = "apb", "spdif";
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dmas = <&dma 2>;
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dma-names = "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx_pin>;
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status = "disabled";
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x2000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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r_ccu: clock@1f01400 {
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compatible = "allwinner,sun8i-a83t-r-ccu";
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reg = <0x01f01400 0x400>;
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clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
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<&ccu 6>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun8i-a83t-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
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<&osc16Md512>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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