mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 16:46:49 +07:00
244 lines
6.4 KiB
C
244 lines
6.4 KiB
C
/*
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* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
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*
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* This is an 64bit optimized version that always keeps the full mmconfig
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* space mapped. This allows lockless config space operation.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <asm/e820.h>
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#include "pci.h"
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/* aperture is up to 256MB but BIOS may reserve less */
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#define MMCONFIG_APER_MIN (2 * 1024*1024)
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#define MMCONFIG_APER_MAX (256 * 1024*1024)
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/* Verify the first 16 busses. We assume that systems with more busses
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get MCFG right. */
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#define MAX_CHECK_BUS 16
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static DECLARE_BITMAP(fallback_slots, 32*MAX_CHECK_BUS);
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/* Static virtual mapping of the MMCONFIG aperture */
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struct mmcfg_virt {
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struct acpi_table_mcfg_config *cfg;
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char __iomem *virt;
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};
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static struct mmcfg_virt *pci_mmcfg_virt;
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static char __iomem *get_virt(unsigned int seg, unsigned bus)
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{
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int cfg_num = -1;
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struct acpi_table_mcfg_config *cfg;
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while (1) {
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++cfg_num;
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if (cfg_num >= pci_mmcfg_config_num)
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break;
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cfg = pci_mmcfg_virt[cfg_num].cfg;
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if (cfg->pci_segment_group_number != seg)
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continue;
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if ((cfg->start_bus_number <= bus) &&
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(cfg->end_bus_number >= bus))
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return pci_mmcfg_virt[cfg_num].virt;
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}
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/* Handle more broken MCFG tables on Asus etc.
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They only contain a single entry for bus 0-0. Assume
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this applies to all busses. */
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cfg = &pci_mmcfg_config[0];
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if (pci_mmcfg_config_num == 1 &&
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cfg->pci_segment_group_number == 0 &&
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(cfg->start_bus_number | cfg->end_bus_number) == 0)
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return pci_mmcfg_virt[0].virt;
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/* Fall back to type 0 */
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return NULL;
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}
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static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
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{
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char __iomem *addr;
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if (seg == 0 && bus < MAX_CHECK_BUS &&
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test_bit(32*bus + PCI_SLOT(devfn), fallback_slots))
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return NULL;
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addr = get_virt(seg, bus);
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if (!addr)
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return NULL;
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return addr + ((bus << 20) | (devfn << 12));
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}
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static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
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*value = -1;
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return -EINVAL;
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}
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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switch (len) {
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case 1:
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*value = readb(addr + reg);
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break;
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case 2:
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*value = readw(addr + reg);
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break;
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case 4:
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*value = readl(addr + reg);
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break;
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}
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return 0;
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}
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static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
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return -EINVAL;
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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switch (len) {
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case 1:
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writeb(value, addr + reg);
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break;
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case 2:
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writew(value, addr + reg);
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break;
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case 4:
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writel(value, addr + reg);
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break;
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}
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return 0;
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}
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static struct pci_raw_ops pci_mmcfg = {
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.read = pci_mmcfg_read,
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.write = pci_mmcfg_write,
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};
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/* K8 systems have some devices (typically in the builtin northbridge)
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that are only accessible using type1
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Normally this can be expressed in the MCFG by not listing them
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and assigning suitable _SEGs, but this isn't implemented in some BIOS.
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Instead try to discover all devices on bus 0 that are unreachable using MM
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and fallback for them. */
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static __init void unreachable_devices(void)
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{
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int i, k;
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/* Use the max bus number from ACPI here? */
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for (k = 0; k < MAX_CHECK_BUS; k++) {
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for (i = 0; i < 32; i++) {
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u32 val1;
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char __iomem *addr;
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pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
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if (val1 == 0xffffffff)
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continue;
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addr = pci_dev_base(0, k, PCI_DEVFN(i, 0));
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if (addr == NULL|| readl(addr) != val1) {
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set_bit(i + 32*k, fallback_slots);
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printk(KERN_NOTICE "PCI: No mmconfig possible"
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" on device %02x:%02x\n", k, i);
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}
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}
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}
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}
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static __init void pci_mmcfg_insert_resources(void)
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{
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#define PCI_MMCFG_RESOURCE_NAME_LEN 19
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int i;
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struct resource *res;
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char *names;
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unsigned num_buses;
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res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
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pci_mmcfg_config_num, GFP_KERNEL);
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if (!res) {
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printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
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return;
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}
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names = (void *)&res[pci_mmcfg_config_num];
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for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
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num_buses = pci_mmcfg_config[i].end_bus_number -
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pci_mmcfg_config[i].start_bus_number + 1;
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res->name = names;
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snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
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pci_mmcfg_config[i].pci_segment_group_number);
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res->start = pci_mmcfg_config[i].base_address;
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res->end = res->start + (num_buses << 20) - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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insert_resource(&iomem_resource, res);
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names += PCI_MMCFG_RESOURCE_NAME_LEN;
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}
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}
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void __init pci_mmcfg_init(int type)
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{
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int i;
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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return;
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acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].base_address == 0))
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return;
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/* Only do this check when type 1 works. If it doesn't work
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assume we run on a Mac and always use MCFG */
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if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].base_address,
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pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
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E820_RESERVED)) {
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printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
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pci_mmcfg_config[0].base_address);
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printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
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return;
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}
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pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL);
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if (pci_mmcfg_virt == NULL) {
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printk("PCI: Can not allocate memory for mmconfig structures\n");
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return;
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}
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for (i = 0; i < pci_mmcfg_config_num; ++i) {
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pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
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pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address,
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MMCONFIG_APER_MAX);
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if (!pci_mmcfg_virt[i].virt) {
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printk("PCI: Cannot map mmconfig aperture for segment %d\n",
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pci_mmcfg_config[i].pci_segment_group_number);
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return;
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}
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printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
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}
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unreachable_devices();
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pci_mmcfg_insert_resources();
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raw_pci_ops = &pci_mmcfg;
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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}
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